GATE ECE Combinational circuits PYQs & Answers

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Combinational circuits

Attempt a question, record the concept and assumptions, then check the available answer. Rework mistakes after revising the relevant concepts. Topic tags can overlap; review the question context.

Questions 1–10 of 19. Imported answers require independent review unless marked reviewed.

Topic practice 19 questionsPage 1 of 2

For the Boolean function

the essential prime implicants are __________.

Your answerChoose one option.

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A 4-bit priority encoder has inputs

, and

in descending order of priority. The two-bit output

is generated as 00, 01, 10, and 11 corresponding to inputs

, and

, respectively. The Boolean expression of the output bit

is ______.

Your answerChoose one option.

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The propagation delay of the

MUX shown in the circuit is 10 ns. Consider the propagation delay of the inverter as 0 ns.

Diagram for Electronics and Communication Engineering question 41

is set to 1 then the output

is ______.

Your answerChoose one option.

a square wave of frequency 100 MHz

a square wave of frequency 50 MHz

constant at 0

constant at 1

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Consider the 2-bit multiplexer (MUX) shown in the figure. For OUTPUT to be the XOR of C and D, the values for

, and

are ____________.

Diagram for Electronics and Communication Engineering question 19

Your answerChoose one option.

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Select the Boolean function(s) equivalent to

, where

and

are Boolean variables, and + denotes logical OR operation.

Your answerSelect all correct options. You can choose more than one.

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Select the correct statement(s) regarding CMOS implementation of NOT gates.

Your answerSelect all correct options. You can choose more than one.

Noise Margin High (

) is always equal to the Noise Margin Low (

), irrespective of the sizing of transistors.

Dynamic power consumption during switching is zero.

For a logical high input under steady state, the nMOSFET is in the linear regime of operation.

Mobility of electrons never influences the switching speed of the NOT gate.

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Consider a Boolean gate (D) where the output

is related to the inputs

and

, where + denotes logical OR operation. The Boolean inputs ‘0’ and ‘1’ are also available separately. Using instances of only D gates and inputs ‘0’ and ‘1’, ______ (select the correct option(s)).

Your answerSelect all correct options. You can choose more than one.

NAND logic can be implemented

OR logic cannot be implemented

NOR logic can be implemented

AND logic cannot be implemented

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A standard CMOS inverter is designed with equal rise and fall times (

). If the width of the PMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin (

) and the HIGH noise margin (

Your answerChoose one option.

increases and

decreases.

decreases and

increases.

Both

and

increase.

No change in the noise margins.

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In the circuit shown, what are the values of F for EN = 0 and EN = 1, respectively?

Diagram for Electronics and Communication Engineering question 14

Your answerChoose one option.

0 and D

Hi-Z and D

0 and 1

Hi-Z and

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In the circuit shown, A and B are the inputs and F is the output. What is the functionality of the circuit?

Diagram for Electronics and Communication Engineering question 15

Your answerChoose one option.

Latch

XNOR

SRAM Cell

XOR

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GATE ECE Combinational circuits PYQs

How to practice Combinational circuits

Question 19

Question 40

Question 41

Question 19

Question 27

Question 28

Question 49

Question 13

Question 14

Question 15