1. Home
  2. GATE
  3. Electronics and Communication Engineering
  4. Topics
  5. concept:critical-path-delay
Electronics and Communication Engineering

GATE ECE concept:critical-path-delay PYQs

Build your understanding with focused practice from past exam papers.

How to practice concept:critical-path-delay

Attempt a question, record the concept and assumptions, then check the available answer. Rework mistakes after revising the relevant concepts. Topic tags can overlap; review the question context.

GATE ECE syllabus

Questions 1–1 of 1. Imported answers require independent review unless marked reviewed.

Topic practice 1 questionsPage 1 of 1

Question 34

Open question
ECNAT1 markNeeds review
For the circuit shown below, the propagation delay of each NAND gate is 1 ns. The critical path delay, in ns, is ______ (rounded off to the nearest integer).
Diagram for Electronics and Communication Engineering question 34


Log in to check the answer

You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answer