Electronics and Communication Engineering
GATE ECE concept:logic-gates PYQs
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How to practice concept:logic-gates
Attempt a question, record the concept and assumptions, then check the available answer. Rework mistakes after revising the relevant concepts. Topic tags can overlap; review the question context.
Questions 1–2 of 2. Imported answers require independent review unless marked reviewed.
Question 23
Open questionECMCQ1 markNeeds review
A 3-input majority logic gate has inputs
,
, and
. The output
of the gate is logic ‘1’ if two or more of the inputs are logic ‘1’. The output
is logic ‘0’ if two or more of the inputs are logic ‘0’. Which one of the following options is a Boolean expression of the output
?Your answerChoose one option.
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Open questionECNAT2 marksNeeds review
The logic gates shown in the digital circuit below use strong pull-down nMOS transistors for LOW logic level at the outputs. When the pull-downs are off, high-value resistors set the output logic levels to HIGH (i.e. the pull-ups are weak). Note that some nodes are intentionally shorted to implement “wired logic”. Such shorted nodes will be HIGH only if the outputs of all the gates whose outputs are shorted are HIGH.
The number of distinct values of
(out of the 16 possible values) that give
is ______.Log in to check the answer
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