Electronics and Communication Engineering
GATE ECE Data converters PYQs
Build your understanding with focused practice from past exam papers.
How to practice Data converters
Attempt a question, record the concept and assumptions, then check the available answer. Rework mistakes after revising the relevant concepts. Topic tags can overlap; review the question context.
Questions 1–7 of 7. Imported answers require independent review unless marked reviewed.
Question 35
Open questionECNAT1 markNeeds review
A 4-bit weighted-resistor DAC with inputs
,
,
, and
(MSB to LSB) is designed using an ideal op amp, as shown below. The switches are closed when the corresponding input bits are logic ‘1’ and open otherwise.When the input
changes from 1110 to 1101, the magnitude of the change in the output voltage
(in mV, rounded off to the nearest integer) is ________. 
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You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 44
Open questionECMCQ2 marksNeeds review
A 10-bit analog-to-digital converter (ADC) has a sampling frequency of 1 MHz and a full scale voltage of 3.3 V.
For an input sinusoidal signal with frequency 500 kHz, the maximum SNR (in dB, rounded off to two decimal places) and the data rate (in Mbps) at the output of the ADC are ________, respectively.
Your answerChoose one option.
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You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 46
Open questionECMCQ2 marksNeeds review
A full scale sinusoidal signal is applied to a 10-bit ADC. The fundamental signal component in the ADC output has a normalized power of 1 W, and the total noise and distortion normalized power is 10 μW. The effective number of bits (rounded off to the nearest integer) of the ADC is ______.
Your answerChoose one option.
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You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 31
Open questionECNAT1 markNeeds review
The signal-to-noise ratio (SNR) of an ADC with a full-scale sinusoidal input is given to be 61.96 dB. The resolution of the ADC is ______ bits (rounded off to the nearest integer).
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You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 62
Open questionECNAT2 marksNeeds review
A sample and hold circuit is implemented using a resistive switch and a capacitor with a time constant of 1
s. The time for the sampling switch to stay closed to charge a capacitor adequately to a full scale voltage of 1 V with 12-bit accuracy is ______
s (rounded off to two decimal places).Log in to check the answer
You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 20
Open questionECNAT1 markNeeds review
An 8-bit unipolar (all analog output values are positive) digital-to-analog converter (DAC) has a full-scale voltage range from 0 V to 7.68 V. If the digital input code is 10010110 (the leftmost bit is MSB), then the analog output voltage of the DAC (rounded off to one decimal place) is __________ V.
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You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 20
Open questionECNAT1 markNeeds review
A 10-bit D/A converter is calibrated over the full range from 0 to 10 V. If the input to the D/A converter is 13A (in hex), the output (rounded off to three decimal places) is ______ V.
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