GATE ECE format:nat PYQs & Answers — Page 20

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Questions 191–200 of 239. Imported answers require independent review unless marked reviewed.

Topic practice 239 questionsPage 20 of 24

A connection is made consisting of resistance A in series with a parallel combination of resistances B and C. Three resistors of value 10 Ω, 5 Ω, 2 Ω are provided. Consider all possible permutations of the given resistors into the positions A, B, C, and identify the configurations with maximum possible overall resistance, and also the ones with minimum possible overall resistance. The ratio of maximum to minimum values of the resistances (up to second decimal place) is __________.

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In the circuit shown, the positive angular frequency

(in radians per second) at which the magnitude of the phase difference between the voltages

and

equals

radians, is ______.

Diagram for Electronics and Communication Engineering question 7

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Consider an

-channel MOSFET having width

, length

, electron mobility in the channel

and oxide capacitance per unit area

. If gate-to-source voltage

, drain-to-source voltage

, threshold voltage

and

, then transconductance

(in mA/V) is _____.

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The output

of the diode circuit shown in the figure is connected to an averaging DC voltmeter. The reading on the DC voltmeter in Volts, neglecting the voltage drop across the diode, is _____.

Diagram for Electronics and Communication Engineering question 12

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Consider the circuit shown in the figure. Assume base-to-emitter voltage

and common-base current gain

of the transistor is unity.

Diagram for Electronics and Communication Engineering question 14

The value of the collector-to-emitter voltage

(in volt) is _____.

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Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output of the latch in percentage is

Diagram for Electronics and Communication Engineering question 17

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The open loop transfer function

where

is an integer, is connected in unity feedback configuration as shown in the figure.

Diagram for Electronics and Communication Engineering question 18

Given that the steady state error is zero for unit step input and is 6 for unit ramp input, the value of the parameter

is __________.

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For the system shown in the figure,

________.

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Consider the state space realization

where

denotes the unit step function. The value of

is ________.

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Let

be independent random variables.

has mean 0 and variance 1, while

has mean 1 and variance 4. The mutual information

between

and

in bits is ________.

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GATE ECE format:nat PYQs

Question 6

Question 7

Question 11

Question 12

Question 14

Question 17

Question 18

Question 18

Question 19

Question 21