GATE ECE kind:question PYQs & Answers — Page 62

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Questions 611–620 of 715. Imported answers require independent review unless marked reviewed.

Topic practice 715 questionsPage 62 of 72

In the figure, D1 is a real silicon

junction diode with a drop of 0.7 V under forward bias condition and D2 is a Zener diode with breakdown voltage of

V. The input

is a periodic square wave of period T, whose one period is shown in the figure.

Diagram for Electronics and Communication Engineering question 13

Assuming

, where

is the time constant of the circuit, the maximum and minimum values of the output waveform are respectively

Your answerChoose one option.

7.5 V and −20.5 V

6.1 V and −21.9 V

7.5 V and −21.2 V

6.1 V and −22.6 V

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The Miller effect in the context of a Common Emitter amplifier explains

Your answerChoose one option.

an increase in the low-frequency cutoff frequency

an increase in the high-frequency cutoff frequency

a decrease in the low-frequency cutoff frequency

a decrease in the high-frequency cutoff frequency

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Consider the circuit shown in the figure. Assume base-to-emitter voltage

and common-base current gain

of the transistor is unity.

Diagram for Electronics and Communication Engineering question 14

The value of the collector-to-emitter voltage

(in volt) is _____.

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In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input condition is: P = Q = ‘0’. If the input condition is changed simultaneously to P = Q = ‘1’, the outputs X and Y are

Diagram for Electronics and Communication Engineering question 15

Your answerChoose one option.

X = ‘1’, Y = ‘1’

either X = ‘1’, Y = ‘0’ or X = ‘0’, Y = ‘1’

either X = ‘1’, Y = ‘1’ or X = ‘0’, Y = ‘0’

X = ‘0’, Y = ‘0’

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For the circuit shown in the figure,

and

are the inputs and

is the output.

The logic implemented by the circuit is

Your answerChoose one option.

XNOR

XOR

NOR

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The clock frequency of an 8085 microprocessor is 5 MHz. If the time required to execute an instruction is 1.4 μs, then the number of T-states needed for executing the instruction is

Your answerChoose one option.

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Consider the circuit shown in the figure.

Diagram for Electronics and Communication Engineering question 16

The Boolean expression

implemented by the circuit is

Your answerChoose one option.

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Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output of the latch in percentage is

Diagram for Electronics and Communication Engineering question 17

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In a DRAM,

Your answerChoose one option.

periodic refreshing is not required

information is stored in a capacitor

information is stored in a latch

both read and write operations can be performed simultaneously

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The open loop transfer function

where

is an integer, is connected in unity feedback configuration as shown in the figure.

Diagram for Electronics and Communication Engineering question 18

Given that the steady state error is zero for unit step input and is 6 for unit ramp input, the value of the parameter

is __________.

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GATE ECE kind:question PYQs

Question 13

Question 14

Question 14

Question 15

Question 15

Question 16

Question 16

Question 17

Question 17

Question 18