Electronics and Communication Engineering
GATE ECE year:2017 PYQs
Build your understanding with focused practice from past exam papers.
Questions 31–40 of 130. Imported answers require independent review unless marked reviewed.
Question 16
Open questionECMCQ1 markNeeds review
The clock frequency of an 8085 microprocessor is 5 MHz. If the time required to execute an instruction is 1.4 μs, then the number of T-states needed for executing the instruction is
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Consider the circuit shown in the figure.

The Boolean expression
implemented by the circuit isYour answerChoose one option.
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Open questionECNAT1 markNeeds review
Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output of the latch in percentage is

.
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In a DRAM,
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Open questionECNAT1 markNeeds review
The open loop transfer function
where
is an integer, is connected in unity feedback configuration as shown in the figure. 
Given that the steady state error is zero for unit step input and is 6 for unit ramp input, the value of the parameter
is __________.Log in to check the answer
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Open questionECNAT1 markNeeds review
For the system shown in the figure,
________. 
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Open questionECMCQ1 markNeeds review
Consider a stable system with transfer function
where
and
are real valued constants. The slope of the Bode log magnitude curve of
converges to
dB/decade as
. A possible pair of values for
and
isYour answerChoose one option.
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Open questionECNAT1 markNeeds review
Consider the state space realization
where
denotes the unit step function. The value of
is ________.Log in to check the answer
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Which of the following can be the pole-zero configuration of a phase-lag controller (lag compensator)?
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Open questionECMCQ1 markNeeds review
Which of the following statements is incorrect?
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