Questions 31–40 of 130. Imported answers require independent review unless marked reviewed.

Topic practice 130 questionsPage 4 of 13

Question 16

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The clock frequency of an 8085 microprocessor is 5 MHz. If the time required to execute an instruction is 1.4 μs, then the number of T-states needed for executing the instruction is
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Question 16

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Consider the circuit shown in the figure.
Diagram for Electronics and Communication Engineering question 16

The Boolean expression

implemented by the circuit is
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Question 17

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ECNAT1 markNeeds review
Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output of the latch in percentage is
Diagram for Electronics and Communication Engineering question 17

.

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Question 17

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In a DRAM,
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Question 18

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ECNAT1 markNeeds review
The open loop transfer function

where

is an integer, is connected in unity feedback configuration as shown in the figure.
Diagram for Electronics and Communication Engineering question 18

Given that the steady state error is zero for unit step input and is 6 for unit ramp input, the value of the parameter

is __________.

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Question 18

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For the system shown in the figure,

________.
Diagram for Electronics and Communication Engineering question 18


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Question 19

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Consider a stable system with transfer function

where

and

are real valued constants. The slope of the Bode log magnitude curve of

converges to

dB/decade as

. A possible pair of values for

and

is
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Question 19

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Consider the state space realization

where

denotes the unit step function. The value of

is ________.

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Question 20

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Which of the following can be the pole-zero configuration of a phase-lag controller (lag compensator)?
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Question 20

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Which of the following statements is incorrect?
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