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Electrical Engineering

GATE EE concept:schmitt-triggers PYQs

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GATE EE syllabus

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Question 52

Open question
EENAT2 marksNeeds review
A CMOS Schmitt-trigger inverter has a low output level of 0 V and a high output level of 5 V. It has input thresholds of 1.6 V and 2.4 V. The input capacitance and output resistance of the Schmitt-trigger are negligible. The frequency of the oscillator shown is ________ Hz. (Round off to 2 decimal places.)
Diagram for Electrical Engineering question 52


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