GATE EE discipline:electrical-electronics-and-instrumentation PYQs & Answers — Page 13

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Questions 121–130 of 715. Imported answers require independent review unless marked reviewed.

Topic practice 715 questionsPage 13 of 72

The op-amps in the following circuit are ideal. The voltage gain of the circuit is _____ (round off to the nearest integer).

Diagram for Electrical Engineering question 56

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The switch (S) closes at

sec. The time, in sec, the capacitor takes to charge to 50 V is _____ (round off to one decimal place).

Diagram for Electrical Engineering question 57

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In an experiment to measure the active power drawn by a single-phase RL Load connected to an AC source through a 2

resistor, three voltmeters are connected as shown in the figure below. The voltmeter readings are as follows:

. Assuming perfect resistors and ideal voltmeters, the Load-active power measured in this experiment, in W, is _______ (round off to one decimal place).

Diagram for Electrical Engineering question 58

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In the Wheatstone bridge shown below, the sensitivity of the bridge in terms of change in balancing voltage

for unit change in the resistance

, in mV/Ω, is ______________ (round off to two decimal places).

Diagram for Electrical Engineering question 59

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The steady state capacitor current of a conventional DC-DC buck converter, working in CCM, is shown in one switching cycle. If the input voltage is 30 V, the value of the inductor used, in mH, is ______________ (round off to one decimal place).

Diagram for Electrical Engineering question 60

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An ideal low pass filter has frequency response given by

. Let

be its time domain representation. Then

_____ (round off to the nearest integer).

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Consider the state-space model

where

are the state, input and output, respectively. The matrices

are given below

The sum of the magnitudes of the poles is ____________ (round off to nearest integer).

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Using shunt capacitors, the power factor of a 3-phase, 4 kV induction motor (drawing 390 kVA at 0.77 pf lag) is to be corrected to 0.85 pf lag. The line current of the capacitor bank, in A, is ____________ (round off to one decimal place).

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Two units, rated at 100 MW and 150 MW, are enabled for economic load dispatch. When the overall incremental cost is 10,000 Rs./MWh, the units are dispatched to 50 MW and 80 MW respectively. At an overall incremental cost of 10,600 Rs./MWh, the power outputs of the units are 80 MW and 92 MW, respectively. The total plant MW-output (without overloading any unit) at an overall incremental cost of 11,800 Rs./MWh is ____________ (round off to the nearest integer).

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A controller

of the form

is to be designed for the plant

as shown in the figure. The value of

that yields a phase margin of

at the gain cross-over frequency of 10 rad/sec is ________________ (round off to one decimal place).

Diagram for Electrical Engineering question 65

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GATE EE discipline:electrical-electronics-and-instrumentation PYQs

Question 56

Question 57

Question 58

Question 59

Question 60

Question 61

Question 62

Question 63

Question 64

Question 65