GATE EE exam:gate PYQs & Answers — Page 49

Questions 481–490 of 715. Imported answers require independent review unless marked reviewed.

Topic practice 715 questionsPage 49 of 72

Given,

is the gate-source voltage,

is the drain source voltage, and

is the threshold voltage of an enhancement type NMOS transistor, the conditions for transistor to be biased in saturation are

Your answerChoose one option.

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A current controlled current source (CCS) has an input impedance of 10

and output impedance of 100 k

. When this CCS is used in a negative feedback closed loop with a loop gain of 9, the closed loop output impedance is

Your answerChoose one option.

100

100 k

1000 k

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, the value of line integral

evaluated over contour

formed by the segments

is _________.

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The current

flowing in the circuit shown below in amperes (round off to one decimal place) is ________.

Diagram for Electrical Engineering question 19

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A co-axial cylindrical capacitor shown in Figure (i) has dielectric with relative permittivity

. When one-fourth portion of the dielectric is replaced with another dielectric of relative permittivity

as shown in Figure (ii), the capacitance is doubled. The value of

is ________.

Diagram for Electrical Engineering question 20

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The

matrix of a two-bus power system having two identical parallel lines connected between them in pu is given as

The magnitude of the series reactance of each line in pu (round off up to one decimal place) is __________.

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Five alternators each rated 5 MVA, 13.2 kV with 25% of reactance on its own base are connected in parallel to a busbar. The short-circuit level in MVA at the bus is___________.

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The total impedance of the secondary winding, leads, and burden of a 5 A CT is 0.01

. If the fault current is 20 times the rated primary current of the CT, the VA output of the CT is __________.

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The rank of the matrix,

, is __________.

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The output voltage of a single-phase full bridge voltage source inverter is controlled by unipolar PWM with one pulse per half cycle. For the fundamental rms component of output voltage to be 75% of DC voltage, the required pulse width in degrees (round off up to one decimal place) is __________.

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GATE EE exam:gate PYQs

Question 16

Question 17

Question 18

Question 19

Question 20

Question 21

Question 22

Question 23

Question 24

Question 25