GATE IN Digital Electronics PYQs & Answers — Page 3

Questions 21–30 of 57. Imported answers require independent review unless marked reviewed.

For the given digital circuit, A = B = 1. Assume that AND, OR, and NOT gates have propagation delays of 10 ns, 10 ns, and 5 ns respectively. All lines have zero propagation delay. Given that C = 1 when the circuit is turned on, the frequency of steady-state oscillation of the output Y is _____.

Diagram for Instrumentation Engineering question 41

Your answerChoose one option.

20 MHz

15 MHz

40 MHz

50 MHz

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In the circuit shown, the initial binary content of shift register A is 1101 and that of shift register B is 1010. The shift registers are positive-edge triggered, and the gates have no delay.

When the shift control is high, what will be the binary content of the shift registers A and B after four clock pulses?

Diagram for Instrumentation Engineering question 42

Your answerChoose one option.

A = 1101, B = 1101

A = 1110, B = 1001

A = 0101, B = 1101

A = 1010, B = 1111

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The logic block shown has an output

given by ______

Diagram for Instrumentation Engineering question 21

Your answerChoose one option.

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The output F of the digital circuit shown can be written in the form(s) ______

Diagram for Instrumentation Engineering question 23

Your answerSelect all correct options. You can choose more than one.

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An analog-to-digital converter with resolution 0.01 V converts analog signals between 0 V to +10 V to an unsigned binary output. The minimum number of bits (in integer) in the output is ______

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A resistor ladder digital-to-analog converter (DAC) receives a digital input that results in the circuit having the state as shown in the figure. For this digital input, the Thevenin voltage,

, and Thevenin resistance,

, as seen at the output node are ________

Your answerChoose one option.

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The digital circuit shown ______

Diagram for Instrumentation Engineering question 46

Your answerChoose one option.

is a divide-by-5 counter

is a divide-by-7 counter

is a divide-by-8 counter

does not function as a counter due to disjoint cycles of states

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and

are two 2-bit unsigned binary numbers. If

is a Boolean function such that

only when

, and

otherwise, then

can be minimized to the form ______

Your answerChoose one option.

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For a 4-bit Flash type Analog to Digital Convertor (ADC) with full scale input voltage range “V”, which of the following statement(s) is/are true?

Your answerSelect all correct options. You can choose more than one.

The ADC requires 15 comparators.

The ADC requires one 4 to 2 priority encoder and 4 comparators.

A change in the input voltage by

will always flip MSB of the output.

A change in the input voltage by

will always flip the LSB of the output.

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A 16-bit microprocessor has twenty address lines (

) and 16 data lines. The higher eight significant lines of the data bus of the processor are tied to the 8-data lines of a 16 Kbyte memory that can store one byte in each of its 16K address locations. The memory chip should map onto contiguous memory locations and occupy only 16 Kbyte of memory space. Which of the following statement(s) is/are correct with respect to the above design:

Your answerSelect all correct options. You can choose more than one.

If the 16 Kbyte of memory chip is mapped with a starting address of 8000H, then the ending address will be 83FFF.

The active high chip-select needed to map the 16 Kbyte memory with a starting address at F000H is given by the logic expression

The 16 Kbyte memory cannot be mapped with contiguous address locations with a starting address as 0F000H using only

for generating chip select.

The above chip cannot be interfaced as the width of the data bus of the processor and the memory chip differs.

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GATE IN Digital Electronics PYQs

Question 41

Question 42

Question 21

Question 23

Question 25

Question 42

Question 46

Question 48

Question 10

Question 11