Instrumentation Engineering
GATE IN Digital Electronics PYQs
Build your understanding with focused practice from past exam papers.
Questions 41–50 of 57. Imported answers require independent review unless marked reviewed.
Question 12
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The circuit shown in the figure below uses ideal positive edge-triggered synchronous J-K flip flops with outputs X and Y. If the initial state of the output is X=0 and Y=0 just before the arrival of the first clock pulse, the state of the output just before the arrival of the second clock pulse is
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An 8-bit weighted resistor digital-to-analog converter (DAC) has the smallest resistance of 500
. The largest resistance has a value ______ k
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The total number of Boolean functions with distinct truth-tables that can be defined over 3 Boolean variables is ______.
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The figure below shows the
full-adder block of a binary adder circuit. Cᵢ is the input carry and Cᵢ₊₁ is the output carry of the circuit. Assume that each logic gate has a delay of 2 nanosecond, with no additional time delay due to the interconnecting wires. If the inputs Aᵢ, Bᵢ are available and stable throughout the carry propagation, the maximum time taken for an input Cᵢ to produce a steady-state output Cᵢ₊₁ is ______ nanosecond. 
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and
are 2-bit binary numbers. The Boolean function S that satisfies the condition “If X > Y, then S = 1”, in its minimized form, isYour answerChoose one option.
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In the circuit below, the light dependent resistor (LDR) receives light from the LED. The LDR has resistances of 5 kΩ and 500 Ω under dark and illuminated conditions, respectively. The LED
is OFF at time
. At time
s, the switch
is closed for 1 ms and then kept open thereafter. Assuming zero propagation delay in the devices, the LEDYour answerChoose one option.
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In a microprocessor with a 16 bit address bus, the most significant address lines A15 to A12 are used to select a 4096 word memory unit, while lines A0 to A11 are used to address a particular word in the memory unit. If the 3 least significant lines of the address bus A0 to A2 are short-circuited to ground, the addressable number of words in the memory unit is ______.
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For the 3-bit binary counter shown in the figure, the output increments at every positive transition in the clock (CLK). Assume ideal diodes and the start state of the counter as 000. If output high is 1 V and output low is 0 V, the current I (in mA) flowing through the 50 Ω resistor during the 5ᵗʰ clock cycle is (up to one decimal place) ______.
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The representation of the decimal number (27.625)₁₀ in base-2 number system is
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The number of comparators required for implementing an 8-bit flash analog-to-digital converter is
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