Computer Science and Information Technology
2017 · Paper 1
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Complete GATE CSE 2017 Paper 1 overview, original pages and practice · Timed previous-paper practice
Questions 52–54 of 65. Imported answers require review unless explicitly marked reviewed.
Question 52
Open questionCSNAT2 marksNeeds review
Consider the expression
. Let X be the minimum number of registers required by an optimal code generation (without any register spill) algorithm for a load/store architecture, in which (i) only load and store instructions can have memory operands and (ii) arithmetic instructions can have only register or immediate operands. The value of X is ________.Log in to check the answer
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Open questionCSNAT2 marksNeeds review
Consider the following C program.
#include<stdio.h>
#include <string.h>
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Open questionCSNAT2 marksNeeds review
A cache memory unit with capacity of
words and block size of
words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ______ bits.Log in to check the answer
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