2024 · Paper 1

Complete GATE CSE 2024 Paper 1 overview, original pages and practice · Timed previous-paper practice

Questions 28–30 of 65. Imported answers require review unless explicitly marked reviewed.

Question 28

Open question

CS1MSQ1 markNeeds review

Consider the circuit shown below where the gates may have propagation delays. Assume that all signal transitions occur instantaneously and that the wires have no delays. Which of the following statements about the circuit is/are CORRECT?



Your answerSelect all correct options. You can choose more than one.

A.

With no propagation delays, the output



is always logic Zero

B.

With no propagation delays, the output



is always logic One

C.

With propagation delays, the output



can have a transient logic One after



transitions from logic Zero to logic One

D.

With propagation delays, the output



can have a transient logic Zero after



transitions from logic One to logic Zero

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Question 29

Open question

CS1MSQ1 markNeeds review

TCP client P successfully establishes a connection to TCP server Q. Let



denote the sequence number in the SYN sent from P to Q. Let



denote the acknowledgement number in the SYN ACK from Q to P. Which of the following statements is/are CORRECT?

Your answerSelect all correct options. You can choose more than one.

A.

The sequence number



is chosen randomly by P

B.

The sequence number



is always 0 for a new connection

C.

The acknowledgement number



is equal to



D.

The acknowledgement number



is equal to $N_P + 1

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Question 30

Open question

CS1MSQ1 markNeeds review

Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?

Your answerSelect all correct options. You can choose more than one.

A.

In a pipelined execution, forwarding means the result from a source stage of an earlier instruction is passed on to the destination stage of a later instruction

B.

In forwarding, data from the output of the MEM stage can be passed on to the input of the EX stage of the next instruction

C.

Forwarding cannot prevent all pipeline stalls

D.

Forwarding does not require any extra hardware to retrieve the data from the pipeline stages

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