GATE CSE 2024 Paper 1 — page 5

Questions 13–15 of 65. Imported answers require review unless explicitly marked reviewed.

Consider a system that uses 5 bits for representing signed integers in 2’s complement format. In this system, two integers

and

are represented as

and

. Which one of the following operations will result in either an arithmetic overflow or an arithmetic underflow?

Your answerChoose one option.

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Consider a permutation sampled uniformly at random from the set of all permutations of

for some

. Let

be the event that 1 occurs before 2 in the permutation, and

the event that 3 occurs before 4. Which one of the following statements is TRUE?

Your answerChoose one option.

The events

and

are mutually exclusive

The events

and

are independent

Either event

must occur

Event

is more likely than event

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Which one of the following statements is FALSE?

Your answerChoose one option.

In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a stolen cycle

For bulk data transfer, the burst mode of DMA has a higher throughput than the cycle stealing mode

Program I/O mechanism has a better CPU utilization than the interrupt driven I/O mechanism

The CPU can start executing in interrupt service routine faster with vectored interrupts than with non-vectored interrupts

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2024 · Paper 1