Computer Science and Information Technology
2025 · Paper 2
Take it one question at a time. Try an answer, then check your understanding.
Complete GATE CSE 2025 Paper 2 overview, original pages and practice · Timed previous-paper practice
Questions 55–57 of 65. Imported answers require review unless explicitly marked reviewed.
Question 55
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Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is 1 nanosecond (ns) and the “hit rate” for L1 cache is 90% while the processor is accessing the data from L1 cache. Whereas, for the second level (L2) cache, the “hit rate” is 80% and the “miss penalty” for transferring data from L2 cache to L1 cache is 10 ns. The “miss penalty” for the data to be transferred from main memory to L2 cache is 100 ns.
Then the average memory access time in this system in nanoseconds is __________. (rounded off to one decimal place)
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A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is __________. (rounded off to two decimal places)
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You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 57
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In a B⁺- tree where each node can hold at most four key values, a root to leaf path consists of the following nodes:
A = (49, 77, 83, -), B = (7, 19, 33, 44), C = (20*, 22*, 25*, 26*)
The *-marked keys signify that these are data entries in a leaf.
Assume that a pointer between keys
and
points to a subtree containing keys in
, and that when a leaf is created, the smallest key in it is copied up into its parent.A record with key value 23 is inserted into the B⁺- tree.
The smallest key value in the parent of the leaf that contains 25* is __________. (Answer in integer)
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