GATE EE 2017 Paper 2 — page 13

Complete GATE EE 2017 Paper 2 overview, original pages and practice · Timed previous-paper practice

Questions 37–39 of 65. Imported answers require review unless explicitly marked reviewed.

Paper practice 65 questionsPage 13 of 22

For the circuit shown in the figure below, it is given that

. The transistor has

and

when the B-E junction is forward biased.

Diagram for Electrical Engineering question 37

For this circuit, the value of

Your answerChoose one option.

121

129

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For the circuit shown below, assume that the OPAMP is ideal.

Diagram for Electrical Engineering question 38

Which one of the following is TRUE?

Your answerChoose one option.

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The figure below shows a half-bridge voltage source inverter supplying an RL-load with

and

. The desired fundamental frequency of the load voltage is 50 Hz. The switch control signals of the converter are generated using sinusoidal pulse width modulation with modulation index,

. At 50 Hz, the RL-load draws an active power of 1.44 kW. The value of DC source voltage

in volts is

Diagram for Electrical Engineering question 39

Your answerChoose one option.

500

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2017 · Paper 2

Question 37

Question 38

Question 39