GATE CSE area:computing-and-data PYQs & Answers — Page 10

Questions 91–100 of 159. Imported answers require independent review unless marked reviewed.

Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the execution of a program, four data words P, Q, R, and S are accessed in that order 10 times (i.e., PQRS PQRS...). Hence, there are 40 accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of P, Q, R, and S are 0x2A2, 0xC28A, 0xCA8A, and 0xA262, respectively. For the execution of the above program, which of the following statements is/are TRUE with respect to the data cache?

Your answerSelect all correct options. You can choose more than one.

Every access to S is a hit.

Once P is brought to the cache it is never evicted.

At the end of the execution only R and S reside in the cache.

Every access to R evicts Q from the cache.

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Consider routing table of an organization’s router shown below:

Subnet Number	Subnet Mask	Next Hop
12.20.164.0	255.255.252.0	R1
12.20.170.0	255.255.254.0	R2
12.20.168.0	255.255.254.0	Interface 0
12.20.166.0	255.255.254.0	Interface 1
default		R3

Which of the following prefixes in CIDR notation can be collectively used to correctly aggregate all of the subnets in the route table?

Your answerSelect all correct options. You can choose more than one.

12.20.164.0/20

12.20.164.0/22

12.20.164.0/21

12.20.168.0/22

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Consider a network with three routers P, Q, R shown in the figure below. All the links have cost of unity.

Diagram for Computer Science and Information Technology question 57

The routers exchange distance vector routing information and have converged on the routing tables, after which the link Q–R fails. Assume that P and Q send out routing updates at random times, at the same average rate. The probability of a routing loop forming (rounded off to one decimal place) between P and Q, leading to count-to-infinity problem, is __________.

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Consider a 100 Mbps link between an earth station (sender) and a satellite (receiver) at an altitude of 2100 km. The signal propagates at a speed of

m/s. The time taken (in milliseconds, rounded off to two decimal places) for the receiver to completely receive a packet of 1000 bytes transmitted by the sender is __________.

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Consider the data transfer using TCP over a 1 Gbps link. Assuming that the maximum segment lifetime (MSL) is set to 60 seconds, the minimum number of bits required for the sequence number field of the TCP header, to prevent the sequence number space from wrapping around during the MSL is __________.

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A processor X₁ operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor X₂ operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for X₁ and X₂. If the BPU has a prediction accuracy of 80%, the speed up (rounded off to two decimal places) obtained by X₂ over X₁ in executing P is __________.

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Consider the three-way handshake mechanism followed during TCP connection establishment between hosts P and Q. Let X and Y be two random 32-bit starting sequence numbers chosen by P and Q respectively. Suppose P sends a TCP connection request message to Q with a TCP segment having SYN bit = 1, SEQ number = X, and ACK bit = 0. Suppose Q accepts the connection request. Which one of the following choices represents the information present in the TCP segment header that is sent by Q to P?

Your answerChoose one option.

SYN bit = 1, SEQ number = X+1, ACK bit = 0, ACK number = Y, FIN bit = 0

SYN bit = 0, SEQ number = X+1, ACK bit = 0, ACK number = Y, FIN bit = 1

SYN bit = 1, SEQ number = Y, ACK bit = 1, ACK number = X+1, FIN bit = 0

SYN bit = 1, SEQ number = Y, ACK bit = 1, ACK number = X, FIN bit = 0

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Consider the following two statements.

: Destination MAC address of an ARP reply is a broadcast address.

: Destination MAC address of an ARP request is a broadcast address.

Which one of the following choices is correct?

Your answerChoose one option.

Both

and

are true.

is true and

is false.

is false and

is true.

Both

and

are false.

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Consider a set-associative cache of size 2KB (1KB =

bytes) with cache block size of 64 bytes. Assume that the cache is byte-addressable and a 32-bit address is used for accessing the cache. If the width of the tag field is 22 bits, the associativity of the cache is ________.

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Consider a computer system with DMA support. The DMA module is transferring one 8-bit character in one CPU cycle from a device to memory through cycle stealing at regular intervals. Consider a 2 MHz processor. If 0.5% processor cycles are used for DMA, the data transfer rate of the device is ________ bits per second.

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GATE CSE area:computing-and-data PYQs

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