GATE CSE area:computing-and-data PYQs & Answers — Page 14

Questions 131–140 of 159. Imported answers require independent review unless marked reviewed.

Consider the following processor design characteristics.

I. Register-to-register arithmetic operations only II. Fixed-length instruction format III. Hardwired control unit

Which of the characteristics above are used in the design of a RISC processor?

Your answerChoose one option.

I and II only

II and III only

I and III only

I, II and III

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The following are some events that occur after a device controller issues an interrupt while process L is under execution.

(P) The processor pushes the process status of L onto the control stack. (Q) The processor finishes the execution of the current instruction. (R) The processor executes the interrupt service routine. (S) The processor pops the process status of L from the control stack. (T) The processor loads the new PC value based on the interrupt.

Which one of the following is the correct order in which the events above occur?

Your answerChoose one option.

QPTS

PTRSQ

TRPQS

QTPRS

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Match the following:

Field	Length in bits
P. UDP Header’s Port Number	I. 48
Q. Ethernet MAC Address	II. 8
R. IPv6 Next Header	III. 32
S. TCP Header’s Sequence Number	IV. 16

Your answerChoose one option.

P-II, Q-IV, R-II, S-I

P-II, Q-I, R-IV, S-III

P-IV, Q-I, R-II, S-III

P-IV, Q-I, R-III, S-II

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Consider the following statements regarding the slow start phase of the TCP congestion control algorithm. Note that cwnd stands for the TCP congestion window and MSS denotes the Maximum Segment Size.

(i) The cwnd increases by 2 MSS on every successful acknowledgement. (ii) The cwnd approximately doubles on every successful acknowledgement. (iii) The cwnd increases by 1 MSS every round trip time. (iv) The cwnd approximately doubles every round trip time.

Which one of the following is correct?

Your answerChoose one option.

Only (ii) and (iii) are true

Only (i) and (iii) are true

Only (iv) is true

Only (i) and (iv) are true

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A 32-bit wide main memory unit with a capacity of 1 GB is built using 256 M × 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is

. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is ________.

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Consider a long-lived TCP session with an end-to-end bandwidth of 1 Gbps (=

bits-per-second). The session starts with a sequence number of 1234. The minimum time (in seconds, rounded to the closest integer) before this sequence number can be used again is ________.

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The size of the physical address space of a processor is

bytes. The word length is

bytes. The capacity of cache memory is

bytes. The size of each cache block is

words. For a

-way set-associative cache memory, the length (in number of bits) of the tag field is

Your answerChoose one option.

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The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB). The IF, ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 35 instructions take 2 clock cycles each, and the remaining 25 instructions take 1 clock cycle each. Assume that there are no data hazards and no control hazards.

The number of clock cycles required for completion of execution of the sequence of instructions is _____.

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A processor has 16 integer registers (R0, R1, ..., R15) and 64 floating point registers (F0, F1, ..., F63). It uses a 2-byte instruction format. There are four categories of instructions: Type-1, Type-2, Type-3, and Type-4. Type-1 category consists of four instructions, each with 3 integer register operands (3Rs). Type-2 category consists of eight instructions, each with 2 floating point register operands (2Fs). Type-3 category consists of fourteen instructions, each with one integer register operand and one floating point register operand (1R+1F). Type-4 category consists of N instructions, each with a floating point register operand (1F).

The maximum value of N is __________.

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Consider an IP packet with a length of 4,500 bytes that includes a 20-byte IPv4 header and a 40-byte TCP header. The packet is forwarded to an IPv4 router that supports a Maximum Transmission Unit (MTU) of 600 bytes. Assume that the length of the IP header in all the outgoing fragments of this packet is 20 bytes. Assume that the fragmentation offset value stored in the first fragment is 0.

The fragmentation offset value stored in the third fragment is _____.

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GATE CSE area:computing-and-data PYQs

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