GATE CSE area:computing-and-data PYQs & Answers — Page 5

Questions 41–50 of 159. Imported answers require independent review unless marked reviewed.

Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is 1 nanosecond (ns) and the “hit rate” for L1 cache is 90% while the processor is accessing the data from L1 cache. Whereas, for the second level (L2) cache, the “hit rate” is 80% and the “miss penalty” for transferring data from L2 cache to L1 cache is 10 ns. The “miss penalty” for the data to be transferred from main memory to L2 cache is 100 ns.

Then the average memory access time in this system in nanoseconds is __________. (rounded off to one decimal place)

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A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is __________. (rounded off to two decimal places)

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Suppose a message of size 1500 bytes is transmitted from a source to a destination using IPv4 protocol via two routers as shown in the figure. Each router has a defined maximum transmission unit (MTU) as shown in the figure, including IP header. The number of fragments that will be delivered to the destination is _______. (Answer in integer)

Diagram for Computer Science and Information Technology question 57

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A computer system supports a logical address space of

bytes. It uses two-level hierarchical paging with a page size of 4096 bytes. A logical address is divided into a

-bit index to the outer page table, an offset within the page of the inner page table, and an offset within the desired page. Each entry of the inner page table uses eight bytes. All the pages in the system have the same size.

The value of

is __________ . (Answer in integer)

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An application executes

number of instructions in 6.3 seconds. There are four types of instructions, the details of which are given in the table. The duration of a clock cycle in nanoseconds is __________. (rounded off to one decimal place)

Instruction type	Clock cycles required per instruction (CPI)	Number of instructions executed
Branch	2
Load	5
Store	4
Arithmetic	3

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Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?

Your answerChoose one option.

2,56,000

3,200

25,60,000

32,000

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Which one of the following statements is FALSE?

Your answerChoose one option.

In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a stolen cycle

For bulk data transfer, the burst mode of DMA has a higher throughput than the cycle stealing mode

Program I/O mechanism has a better CPU utilization than the interrupt driven I/O mechanism

The CPU can start executing in interrupt service routine faster with vectored interrupts than with non-vectored interrupts

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A user starts browsing a webpage hosted at a remote server. The browser opens a single TCP connection to fetch the entire webpage from the server. The webpage consists of a top-level index page with multiple embedded image objects. Assume that all caches (e.g., DNS cache, browser cache) are all initially empty. The following packets leave the user’s computer in some order. (i) HTTP GET request for the index page (ii) DNS request to resolve the web server’s name to its IP address (iii) HTTP GET request for an image object (iv) TCP SYN to open a connection to the web server Which one of the following is the CORRECT chronological order (earliest in time to latest) of the packets leaving the computer?

Your answerChoose one option.

(iv), (ii), (iii), (i)

(ii), (iv), (iii), (i)

(ii), (iv), (i), (iii)

(iv), (ii), (i), (iii)

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Node X has a TCP connection open to node Y. The packets from X to Y go through an intermediate IP router R. Ethernet switch S is the first switch on the network path between X and R. Consider a packet sent from X to Y over this connection.

Which of the following statements is/are TRUE about the destination IP and MAC addresses on this packet at the time it leaves X?

Your answerSelect all correct options. You can choose more than one.

The destination IP address is the IP address of R

The destination IP address is the IP address of Y

The destination MAC address is the MAC address of S

The destination MAC address is the MAC address of Y

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Which of the following tasks is/are the responsibility/responsibilities of the memory management unit (MMU) in a system with paging-based memory management?

Your answerSelect all correct options. You can choose more than one.

Allocate a new page table for a newly created process

Translate a virtual address to a physical address using the page table

Raise a trap when a virtual address is not found in the page table

Raise a trap when a process tries to write to a page marked with read-only permission in the page table

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GATE CSE area:computing-and-data PYQs

Question 55

Question 56

Question 57

Question 58

Question 61

Question 11

Question 15

Question 16

Question 23

Question 24