GATE CSE Computer Organization and Architecture PYQs & Answers — Page 6

Questions 51–60 of 87. Imported answers require independent review unless marked reviewed.

Consider a digital display system (DDS) shown in the figure that displays the contents of register X. A 16-bit code word is used to load a word in X, either from S or from R. S is a 1024-word memory segment and R is a 32-word register file. Based on the value of mode bit M, T selects an input word to load in X. P and Q interface with the corresponding bits in the code word to choose the addressed word. Which one of the following represents the functionality of P, Q, and T?

Diagram for Computer Science and Information Technology question 40

Your answerChoose one option.

P is 10:1 multiplexer; Q is 5:1 multiplexer; T is 2:1 multiplexer

P is 10:2^10 decoder; Q is 5:2^5 decoder; T is 2:1 encoder

P is 10:2^10 decoder; Q is 5:2^5 decoder; T is 2:1 multiplexer

P is 1:10 de-multiplexer; Q is 1:5 de-multiplexer; T is 2:1 multiplexer

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Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the execution of a program, four data words P, Q, R, and S are accessed in that order 10 times (i.e., PQRS PQRS...). Hence, there are 40 accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of P, Q, R, and S are 0x2A2, 0xC28A, 0xCA8A, and 0xA262, respectively. For the execution of the above program, which of the following statements is/are TRUE with respect to the data cache?

Your answerSelect all correct options. You can choose more than one.

Every access to S is a hit.

Once P is brought to the cache it is never evicted.

At the end of the execution only R and S reside in the cache.

Every access to R evicts Q from the cache.

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A processor X₁ operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor X₂ operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for X₁ and X₂. If the BPU has a prediction accuracy of 80%, the speed up (rounded off to two decimal places) obtained by X₂ over X₁ in executing P is __________.

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Consider a set-associative cache of size 2KB (1KB =

bytes) with cache block size of 64 bytes. Assume that the cache is byte-addressable and a 32-bit address is used for accessing the cache. If the width of the tag field is 22 bits, the associativity of the cache is ________.

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Consider a computer system with DMA support. The DMA module is transferring one 8-bit character in one CPU cycle from a device to memory through cycle stealing at regular intervals. Consider a 2 MHz processor. If 0.5% processor cycles are used for DMA, the data transfer rate of the device is ________ bits per second.

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Consider a computer system with a byte-addressable primary memory of size

bytes. Assume the computer system has a direct-mapped cache of size 32 KB (1 KB =

bytes), and each cache block is of size 64 bytes. The size of the tag field is ________ bits.

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Assume a two-level inclusive cache hierarchy, L1 and L2, where L2 is the larger of the two. Consider the following statements.

: Read misses in a write through L1 cache do not result in writebacks of dirty lines to the L2.

: Write allocate policy must be used in conjunction with write through caches and no-write allocate policy is used with writeback caches.

Which of the following statements is correct?

Your answerChoose one option.

is true and

is false

is false and

is true

is true and

is true

is false and

is false

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If the numerical value of a 2-byte signed integer on a little endian computer is 255 more than that on a big endian computer, which of the following choices represent(s) the unsigned integer on a little endian computer?

Your answerSelect all correct options. You can choose more than one.

0x665

0x001

0x423

0x100

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Consider a three-level page table to translate a 39-bit virtual address to a physical address as shown below.

Diagram for Computer Science and Information Technology question 48

The page size is 4KB (1KB =

bytes) and page table entry size at every level is 8 bytes. A process

is currently using 2GB (1GB =

bytes) virtual memory which is mapped to 2GB of physical memory. The minimum amount of memory required for the page table of

across all levels is ______ KB.

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A five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds. The registers that are used between the pipeline stages have a delay of 5 nanoseconds each. The total time to execute 100 independent instructions on this pipeline, assuming there are no pipeline stalls, is __________ nanoseconds.

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GATE CSE Computer Organization and Architecture PYQs

Question 40

Question 54

Question 61

Question 19

Question 20

Question 22

Question 27

Question 44

Question 48

Question 53