GATE CSE Computer Organization and Architecture PYQs & Answers — Page 8

Questions 71–80 of 87. Imported answers require independent review unless marked reviewed.

Assume that in a certain computer, the virtual addresses are 64 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 8 kB and the word size is 4 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 128 valid entries. At most how many distinct virtual addresses can be translated without any TLB miss?

Your answerChoose one option.

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A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a 60-MHz clock. To service a cache miss, the memory controller first takes 1 cycle to accept the starting address of the block, it then takes 3 cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of 1 word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is ________ × 10⁶ bytes/sec.

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Consider the following processor design characteristics.

I. Register-to-register arithmetic operations only II. Fixed-length instruction format III. Hardwired control unit

Which of the characteristics above are used in the design of a RISC processor?

Your answerChoose one option.

I and II only

II and III only

I and III only

I, II and III

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The following are some events that occur after a device controller issues an interrupt while process L is under execution.

(P) The processor pushes the process status of L onto the control stack. (Q) The processor finishes the execution of the current instruction. (R) The processor executes the interrupt service routine. (S) The processor pops the process status of L from the control stack. (T) The processor loads the new PC value based on the interrupt.

Which one of the following is the correct order in which the events above occur?

Your answerChoose one option.

QPTS

PTRSQ

TRPQS

QTPRS

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A 32-bit wide main memory unit with a capacity of 1 GB is built using 256 M × 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is

. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is ________.

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The size of the physical address space of a processor is

bytes. The word length is

bytes. The capacity of cache memory is

bytes. The size of each cache block is

words. For a

-way set-associative cache memory, the length (in number of bits) of the tag field is

Your answerChoose one option.

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The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB). The IF, ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 35 instructions take 2 clock cycles each, and the remaining 25 instructions take 1 clock cycle each. Assume that there are no data hazards and no control hazards.

The number of clock cycles required for completion of execution of the sequence of instructions is _____.

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A processor has 16 integer registers (R0, R1, ..., R15) and 64 floating point registers (F0, F1, ..., F63). It uses a 2-byte instruction format. There are four categories of instructions: Type-1, Type-2, Type-3, and Type-4. Type-1 category consists of four instructions, each with 3 integer register operands (3Rs). Type-2 category consists of eight instructions, each with 2 floating point register operands (2Fs). Type-3 category consists of fourteen instructions, each with one integer register operand and one floating point register operand (1R+1F). Type-4 category consists of N instructions, each with a floating point register operand (1F).

The maximum value of N is __________.

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Consider the C struct defined below:

struct data {

int marks[100];

char grade;

int cnumber;

};

struct data student;

The base address of student is available in register R1. The field student.grade can be accessed efficiently using

Your answerChoose one option.

Post-increment addressing mode, (R1)+

Pre-decrement addressing mode, −(R1)

Index addressing mode, X(R1), where X is an offset represented in 2’s complement 16-bit representation.

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Consider a two-level cache hierarchy with L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache is 0.1; the L2 cache experiences, on average, 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is ____________.

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GATE CSE Computer Organization and Architecture PYQs

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