Computer Science and Information Technology
GATE CSE concept:pipeline-hazards PYQs
Build your understanding with focused practice from past exam papers.
How to practice concept:pipeline-hazards
Attempt a question, record the concept and assumptions, then check the available answer. Rework mistakes after revising the relevant concepts. Topic tags can overlap; review the question context.
Questions 1–3 of 3. Imported answers require independent review unless marked reviewed.
Question 57
Open questionCS2NAT2 marksNeeds review
A non-pipelined instruction execution unit that operates at 1.6 GHz clock takes an average of 5 clock cycles to complete the execution of an instruction. To improve the performance, the system was pipelined with a goal of achieving an average throughput of one instruction per clock cycle. However, it could operate only at 1.2 GHz due to pipeline overheads. While executing a program in the pipelined design, 30% of instructions encountered a stall of 2 cycles due to pipeline hazards. The speed-up obtained by the pipelined design over the non-pipelined one for this program is __________. (rounded off to two decimal places)
Note: 1G=10⁹
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You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 33
Open questionCSNAT1 markNeeds review
Consider a 3-stage pipelined processor having a delay of 10 ns (nanoseconds), 20 ns, and 14 ns, for the first, second, and the third stages, respectively. Assume that there is no other delay and the processor does not suffer from any pipeline hazards. Also assume that one instruction is fetched every cycle.
The total execution time for executing 100 instructions on this processor is _____ ns.
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You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 61
Open questionCSNAT2 marksNeeds review
A processor X₁ operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor X₂ operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for X₁ and X₂. If the BPU has a prediction accuracy of 80%, the speed up (rounded off to two decimal places) obtained by X₂ over X₁ in executing P is __________.
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