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Computer Science and Information Technology

GATE CSE format:nat PYQs

Build your understanding with focused practice from past exam papers.

Questions 261–270 of 281. Imported answers require independent review unless marked reviewed.

Topic practice 281 questionsPage 27 of 29

Question 45

Open question
CSNAT2 marksNeeds review
The read access times and the hit ratios for different caches in a memory hierarchy are as given below.
Cache
Read access time (in nanoseconds)
Hit ratio
I-cache
2
0.8
D-cache
2
0.9
L2-cache
8
0.9
The read access time of main memory is 90 nanoseconds. Assume that the caches use the referred-word-first read policy and the write back policy. Assume that all the caches are direct mapped caches. Assume that the dirty bit is always 0 for all the blocks in the caches. In execution of a program, 60% of memory reads are for instruction fetch and 40% are for memory operand fetch. The average read access time in nanoseconds (up to 2 decimal places) is __________.

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Question 46

Open question
CSNAT2 marksNeeds review
Consider a database that has the relation schema CR(StudentName, CourseName). An instance of the schema CR is as given below.
StudentName
CourseName
SA
CA
SA
CB
SA
CC
SB
CB
SB
CC
SC
CA
SC
CB
SC
CC
SD
CA
SD
CB
SD
CC
SD
CD
SE
CD
SE
CA
SE
CB
SF
CA
SF
CB
SF
CC
The following query is made on the database


The number of rows in

is __________.

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Question 46

Open question
CSNAT2 marksNeeds review
Consider the following database table named

.
player
country
goals
Klose
Germany
16
Ronaldo
Brazil
15
G Müller
Germany
14
Fontaine
France
13
Pelé
Brazil
12
Klinsmann
Germany
11
Kocsis
Hungary
11
Batistuta
Argentina
10
Cubillas
Peru
10
Lato
Poland
10
Lineker
England
10
T Müller
Germany
10
Rahn
Germany
10
Consider the following SQL query:
SELECT ta.player FROM top_scorer AS ta
WHERE ta.goals >ALL (SELECT tb.goals
FROM top_scorer AS tb
WHERE tb.country = 'Spain')
AND ta.goals >ANY (SELECT tc.goals
FROM top_scorer AS tc
WHERE tc.country = 'Germany')
The number of tuples returned by the above SQL query is __________.

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Question 47

Open question
CSNAT2 marksNeeds review
The number of integers between 1 and 500 (both inclusive) that are divisible by 3 or 5 or 7 is __________.

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Question 47

Open question
CSNAT2 marksNeeds review
If the ordinary generating function of a sequence

is

, then

is equal to __________.

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Question 48

Open question
CSNAT2 marksNeeds review
Let

be an array of 31 numbers consisting of a sequence of 0’s followed by a sequence of 1’s. The problem is to find the smallest index

such that

is 1 by probing the minimum number of locations in

. The worst case number of probes performed by an optimal algorithm is __________.

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Question 48

Open question
CSNAT2 marksNeeds review
If a random variable

has a Poisson distribution with mean 5, then the expectation

equals __________.

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Question 49

Open question
CSNAT2 marksNeeds review
Consider a RISC machine where each instruction is exactly 4 bytes long. Conditional and unconditional branch instructions use PC-relative addressing mode with Offset specified in bytes to the target location of the branch instruction. Further the Offset is always with respect to the address of the next instruction in the program sequence. Consider the following instruction sequence
Instr. No.
Instruction
i
add R2, R3, R4
i+1
sub R5, R6, R7
i+2
cmp R1, R9, R10
i+3
beq R1, Offset
If the target of the branch instruction is i, then the decimal value of the Offset is __________.

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Question 49

Open question
CSNAT2 marksNeeds review
In a B+ tree, if the search-key value is 8 bytes long, the block size is 512 bytes and the block pointer size is 2 bytes, then the maximum order of the B+ tree is __________.

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Question 50

Open question
CSNAT2 marksNeeds review
Instruction execution in a processor is divided into 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10, and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns. Two pipelined implementations of the processor are compiled: (i) a naive pipeline implementation (NP) with 5 stages and (ii) an efficient pipeline (EP) where the OF stage is divided into stages OF1 and OF2 with execution times of 12 ns and 8 ns respectively.
The speedup (correct to two decimal places) achieved by EP over NP in executing 20 independent instructions with no hazards is __________.

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