GATE CSE topic:computer-organization-and-architecture PYQs & Answers — Page 3

Questions 21–30 of 87. Imported answers require independent review unless marked reviewed.

A computer has a memory hierarchy consisting of two-level cache (L1 and L2) and a main memory. If the processor needs to access data from memory, it first looks into L1 cache. If the data is not found in L1 cache, it goes to L2 cache. If it fails to get the data from L2 cache, it goes to main memory, where the data is definitely available. Hit rates and access times of various memory units are shown in the figure. The average memory access time in nanoseconds (ns) is ______. (rounded off to two decimal places)

Diagram for Computer Science and Information Technology question 53

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Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is 1 nanosecond (ns) and the “hit rate” for L1 cache is 90% while the processor is accessing the data from L1 cache. Whereas, for the second level (L2) cache, the “hit rate” is 80% and the “miss penalty” for transferring data from L2 cache to L1 cache is 10 ns. The “miss penalty” for the data to be transferred from main memory to L2 cache is 100 ns.

Then the average memory access time in this system in nanoseconds is __________. (rounded off to one decimal place)

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A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is __________. (rounded off to two decimal places)

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A computer system supports a logical address space of

bytes. It uses two-level hierarchical paging with a page size of 4096 bytes. A logical address is divided into a

-bit index to the outer page table, an offset within the page of the inner page table, and an offset within the desired page. Each entry of the inner page table uses eight bytes. All the pages in the system have the same size.

The value of

is __________ . (Answer in integer)

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An application executes

number of instructions in 6.3 seconds. There are four types of instructions, the details of which are given in the table. The duration of a clock cycle in nanoseconds is __________. (rounded off to one decimal place)

Instruction type	Clock cycles required per instruction (CPI)	Number of instructions executed
Branch	2
Load	5
Store	4
Arithmetic	3

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Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?

Your answerChoose one option.

2,56,000

3,200

25,60,000

32,000

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Which one of the following statements is FALSE?

Your answerChoose one option.

In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a stolen cycle

For bulk data transfer, the burst mode of DMA has a higher throughput than the cycle stealing mode

Program I/O mechanism has a better CPU utilization than the interrupt driven I/O mechanism

The CPU can start executing in interrupt service routine faster with vectored interrupts than with non-vectored interrupts

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Which of the following tasks is/are the responsibility/responsibilities of the memory management unit (MMU) in a system with paging-based memory management?

Your answerSelect all correct options. You can choose more than one.

Allocate a new page table for a newly created process

Translate a virtual address to a physical address using the page table

Raise a trap when a virtual address is not found in the page table

Raise a trap when a process tries to write to a page marked with read-only permission in the page table

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Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?

Your answerSelect all correct options. You can choose more than one.

In a pipelined execution, forwarding means the result from a source stage of an earlier instruction is passed on to the destination stage of a later instruction

In forwarding, data from the output of the MEM stage can be passed on to the input of the EX stage of the next instruction

Forwarding cannot prevent all pipeline stalls

Forwarding does not require any extra hardware to retrieve the data from the pipeline stages

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An instruction format has the following structure:

Instruction Number: Opcode destination reg, source reg-1, source reg-2

Consider the following sequence of instructions to be executed in a pipelined processor:

I1: DIV R3, R1, R2

I2: SUB R5, R3, R4

I3: ADD R3, R5, R6

I4: MUL R7, R3, R8

Which of the following statements is/are TRUE?

Your answerSelect all correct options. You can choose more than one.

There is a RAW dependency on R3 between I1 and I2

There is a WAR dependency on R3 between I1 and I3

There is a RAW dependency on R3 between I2 and I3

There is a WAW dependency on R3 between I3 and I4

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GATE CSE topic:computer-organization-and-architecture PYQs

Question 53

Question 55

Question 56

Question 58

Question 61

Question 11

Question 15

Question 24

Question 30

Question 31