GATE ECE branch:ec PYQs & Answers — Page 58

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Questions 571–580 of 715. Imported answers require independent review unless marked reviewed.

Topic practice 715 questionsPage 58 of 72

For a unity feedback control system with the forward path transfer function

The peak resonant magnitude

of the closed-loop frequency response is 2. The corresponding value of the gain

(correct to two decimal places) is ________.

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The figure below shows the Bode magnitude and phase plots of a stable transfer function

Diagram for Electronics and Communication Engineering question 42

Consider the negative unit feedback configuration with gain

in the feedback path. The closed loop is stable for

. The maximum value of

is ______.

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In the circuit shown below, the

value for M

is twice that for M

. The two nMOS transistors are otherwise identical. The threshold voltage

for both transistors is 1.0 V. Note that

for M

must be

Diagram for Electronics and Communication Engineering question 43

Current through the nMOS transistors can be modeled as

The voltage (in volts, accurate to two decimal places) at

is ______.

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A solar cell of area 1.0 cm

, operating at 1.0 sun intensity, has a short circuit current of 20 mA, and an open circuit voltage of 0.65 V. Assuming room temperature operation and thermal equivalent voltage of 26 mV, the open circuit voltage (in volts, correct to two decimal places) at 0.2 sun intensity is ______.

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A junction is made between p

Si with doping density

and p Si with doping density

Given: Boltzmann constant

, electronic charge

. Assume 100% acceptor ionization.

At room temperature (

K), the magnitude of the built-in potential (in volts, correct to two decimal places) across this junction will be __________________.

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In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data

using clock

. The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for logic LOW levels. The data bit and clock periods are equal and the value of

, where the parameters

and

are shown in the figure. Assume that the Flip-Flop and the XOR gate are ideal.

Diagram for Electronics and Communication Engineering question 46

If the probability of input data bit (

) transition in each clock period is 0.3, the average value (in volts, accurate to two decimal places) of the voltage at node

, is ________.

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The logic gates shown in the digital circuit below use strong pull-down nMOS transistors for LOW logic level at the outputs. When the pull-downs are off, high-value resistors set the output logic levels to HIGH (i.e. the pull-ups are weak). Note that some nodes are intentionally shorted to implement “wired logic”. Such shorted nodes will be HIGH only if the outputs of all the gates whose outputs are shorted are HIGH.

Diagram for Electronics and Communication Engineering question 47

The number of distinct values of

(out of the 16 possible values) that give

is ______.

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The cutoff frequency of TE

mode of an air filled rectangular waveguide having inner dimensions

cm (

) is twice that of the dominant TE

mode. When the waveguide is operated at a frequency which is 25% higher than the cutoff frequency of the dominant mode, the guide wavelength is found to be 4 cm. The value of

(in cm, correct to two decimal places) is ______.

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A uniform plane wave traveling in free space and having the electric field

is incident on a dielectric medium (relative permittivity > 1, relative permeability = 1) as shown in the figure and there is no reflected wave.

Diagram for Electronics and Communication Engineering question 49

The relative permittivity (correct to two decimal places) of the dielectric medium is __________.

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The position of a particle

is described by the differential equation:

The initial conditions are

and

. The position (accurate to two decimal places) of the particle at

is ______.

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GATE ECE branch:ec PYQs

Question 41

Question 42

Question 43

Question 44

Question 45

Question 46

Question 47

Question 48

Question 49

Question 50