Electronics and Communication Engineering
GATE ECE concept:hold-time PYQs
Build your understanding with focused practice from past exam papers.
How to practice concept:hold-time
Attempt a question, record the concept and assumptions, then check the available answer. Rework mistakes after revising the relevant concepts. Topic tags can overlap; review the question context.
Questions 1–2 of 2. Imported answers require independent review unless marked reviewed.
Question 62
Open questionECNAT2 marksNeeds review
In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns.
The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is __________.
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Open questionECNAT2 marksNeeds review
For the components in the sequential circuit shown below,
is the propagation delay,
is the setup time, and
is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is ____ MHz. 
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