GATE ECE · 2025 · EC
Question 62: Sequential circuits
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Question 62
ECNAT2 marksNeeds review
In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns.
The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is __________.
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2025EC
GATE ECE 2025 · Paper 1
Electronics and Communication Engineering · Original paper archive
- Section
- Electronics and Communication Engineering
- Question type
- Numerical answer (NAT)
- Marks
- 2 marks
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