Electronics and Communication Engineering
GATE ECE concept:shift-registers PYQs
Build your understanding with focused practice from past exam papers.
How to practice concept:shift-registers
Attempt a question, record the concept and assumptions, then check the available answer. Rework mistakes after revising the relevant concepts. Topic tags can overlap; review the question context.
Questions 1–2 of 2. Imported answers require independent review unless marked reviewed.
Question 49
Open questionECMCQ2 marksNeeds review
A shift-left Shift Register (SR) and a D flip-flop are connected to a synchronized clock as shown in the Figure. Assume that the SR and D flip-flops are initially cleared and the XOR gate has no propagation delay.
Which of the following options gives the correct binary representation (
) of the content of the shift register immediately after the 5th clock transition (positive edge)? 
Your answerChoose one option.
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Open questionECNAT2 marksNeeds review
A 4-bit shift register circuit configured for right-shift operation, i.e.
,
,
,
, is shown. If the present state of the shift register is
, the number of clock cycles required to reach the state
is ____________. 
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