GATE ECE · 2026 · EC
Question 49: Sequential circuits
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Question 49
ECMCQ2 marksNeeds review
A shift-left Shift Register (SR) and a D flip-flop are connected to a synchronized clock as shown in the Figure. Assume that the SR and D flip-flops are initially cleared and the XOR gate has no propagation delay.
Which of the following options gives the correct binary representation (
) of the content of the shift register immediately after the 5th clock transition (positive edge)? 
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2026EC
GATE ECE 2026 · Paper 1
Electronics and Communication Engineering · Original paper archive
- Section
- Electronics and Communication Engineering
- Question type
- Multiple choice (MCQ)
- Marks
- 2 marks
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