GATE CSE 2020 Paper 1 — page 5

Questions 13–15 of 65. Imported answers require review unless explicitly marked reviewed.

Consider the following statements.

I. Daisy chaining is used to assign priorities in attending interrupts. II. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt. III. In polling, the CPU periodically checks the status bits to know if any device needs its attention. IV. During DMA, both the CPU and DMA controller can be bus masters at the same time.

Which of the above statements is/are TRUE?

Your answerChoose one option.

I and II only

I and IV only

I and III only

III only

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Consider the following data path diagram.

Consider an instruction: R0 ← R1 + R2. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts r and w indicate read and write operations, respectively.

R2ᵣ, TEMP1ᵣ, ALUₐdd, TEMP2w

R1ᵣ, TEMP1w

PCᵣ, MARw, MEMᵣ

TEMP2ᵣ, R0w

MDRᵣ, IRw

Which one of the following is the correct order of execution of the above steps?

Diagram for Computer Science and Information Technology question 4

Your answerChoose one option.

2, 1, 4, 5, 3

1, 2, 4, 3, 5

3, 5, 2, 1, 4

3, 5, 1, 2, 4

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The preorder traversal of a binary search tree is 15, 10, 12, 11, 20, 18, 16, 19.

Which one of the following is the postorder traversal of the tree?

Your answerChoose one option.

10, 11, 12, 15, 16, 18, 19, 20

11, 12, 10, 16, 19, 18, 20, 15

20, 19, 18, 16, 15, 12, 11, 10

19, 16, 18, 20, 11, 12, 10, 15

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2020 · Paper 1

Question 3

Question 4

Question 5