GATE CSE · 2020 · CS
Question 3: Computer Organization and Architecture
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Question 3
CSMCQ1 markNeeds review
Consider the following statements.
I. Daisy chaining is used to assign priorities in attending interrupts.
II. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.
III. In polling, the CPU periodically checks the status bits to know if any device needs its attention.
IV. During DMA, both the CPU and DMA controller can be bus masters at the same time.
Which of the above statements is/are TRUE?
Your answerChoose one option.
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2020CS
GATE CSE 2020 · Paper 1
Computer Science and Information Technology · Original paper archive
- Section
- Computer Science and Information Technology
- Question type
- Multiple choice (MCQ)
- Marks
- 1 mark
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