GATE CSE Computer Organization and Architecture PYQs & Answers

Questions 1–10 of 87. Imported answers require independent review unless marked reviewed.

Match each addressing mode in List I with a data element or an element of a data structure (in a high-level language) in List II.

List I: P. Immediate; Q. Indirect; R. Base with index; S. Base with offset/displacement.

List II: 1. Element of an array; 2. Pointer; 3. Element of a record; 4. Constant

Your answerChoose one option.

P–4, Q–3, R–1, S–2

P–4, Q–2, R–1, S–3

P–1, Q–4, R–3, S–2

P–2, Q–3, R–1, S–4

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Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destination operand.

Which one of the following sequences of instructions corresponds to the high-level language statement Z = X + Y?

Note: X, Y, and Z are memory operands. R0, R1, and R2 are registers.

Your answerChoose one option.

ADD Z, X, Y

LOAD R0, X ADD Z, R0, Y

ADD R0, X, Y STORE Z, R0

LOAD R0, X LOAD R1, Y ADD R2, R0, R1 STORE Z, R2

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Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?

Your answerChoose one option.

Read-after-read

Read-after-write

Write-after-read

Write-after-write

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Consider the following two statements about interrupt handling mechanisms in a CPU.

S1: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Service Routine (ISR) when compared to that in a vectored interrupt mechanism.

S2: In daisy-chain interrupt mechanism, the CPU polls all the input devices individually to determine the source of the interrupt.

Which one of the following options is correct with respect to S1 and S2?

Your answerChoose one option.

Both S1 and S2 are true

Both S1 and S2 are false

S1 is true and S2 is false

S1 is false and S2 is true

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Consider the real valued variables X, Y and Z represented using the IEEE 754 single-precision floating-point format. The binary representations of X and Y in hexadecimal notation are as follows:

X: 35C00000 Y: 34A00000

Let

Which one of the following is the binary representation of Z, in hexadecimal notation?

Your answerChoose one option.

35C80000

35CC0000

35E80000

35EC0000

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The size of the physical address space of a processor is

bytes. The capacity of a cache memory unit is

bytes. The cache block size is 128 bytes. The cache memory unit can be built as a direct mapped cache or as a

-way set-associative cache, where

and

. Let the length of the TAG field be

bits for the direct mapped cache, and

bits for the set-associative cache.

Which one of the following options is true?

Your answerChoose one option.

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Consider a processor that has 16 general purpose registers and it uses 2-byte instruction format for all its instructions. Variable-sized opcodes are permitted. There are three different types of instructions; M-type, R-type, and C-type. Each M-type instruction has 2 register operands and a 6-bit immediate operand. Each R-type instruction has 3 register operands. Each C-type instruction has a register operand and a 6-bit offset value. If there are 2 unique M-type opcodes and 7 unique R-type opcodes, which one of the following options gives the maximum number of unique opcodes possible for C-type instructions?

Your answerChoose one option.

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Consider a system with a processor and a 4 KB direct mapped cache with block size of 16 bytes. The system has a 16 MB physical memory. Four words P, Q, R, and S are accessed by the processor in the same order 10 times. That is, there are a total of 40 memory references in the sequence P, Q, R, S, P, Q, R, S,...

Assume that the cache memory is initially empty. The physical addresses of the words are given below (1 word =1 byte).

P: 0x845B32, Q: 0x845B26, R: 0x845B36, S: 0x846B32

Which of the following statements is/are true?

Note: 1K=2¹⁰ and 1M=2²⁰

Your answerSelect all correct options. You can choose more than one.

Every access to P results in a cache miss

Every access to R results in a cache hit

Every access to Q results in a cache miss

Except the first access to S, all subsequent accesses to S result in cache hits

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Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a translation lookaside buffer (TLB). Assume that when a page is evicted from the main memory, the corresponding blocks in the cache are marked as invalid.

For a given memory reference, which of the following sequences of events can NEVER happen?

Your answerSelect all correct options. You can choose more than one.

TLB miss, Page table hit, Cache hit

TLB hit, Page table miss, Cache hit

TLB miss, Page table miss, Cache hit

TLB miss, Page table miss, Cache miss

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A system has a Translation Lookaside Buffer (TLB) that has a reach of 1 MB. TLB reach is defined as the total amount of physical memory that can be accessed through the TLB entries. The paging system uses pages of size 4 KB. The virtual address space is 64 GB and physical address space is 1 GB. If each TLB entry stores a 4-bit process id, page number, frame number, and a 2-bit control field, then the size of the TLB (in bytes) is __________. (answer in integer)

Note: 1K=2¹⁰, 1M=2²⁰, 1G=2³⁰

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GATE CSE Computer Organization and Architecture PYQs

How to practice Computer Organization and Architecture

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