GATE CSE · 2026 · CS
Question 54: Computer Organization and Architecture
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Question 54
CSMSQ2 marksNeeds review
Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a translation lookaside buffer (TLB). Assume that when a page is evicted from the main memory, the corresponding blocks in the cache are marked as invalid.
For a given memory reference, which of the following sequences of events can NEVER happen?
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2026CS
GATE CSE 2026 · Paper 1
Computer Science and Information Technology · Original paper archive
- Section
- Computer Science and Information Technology
- Question type
- Multiple select (MSQ)
- Marks
- 2 marks
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