GATE CSE concept:cache PYQs & Answers

Questions 1–10 of 30. Imported answers require independent review unless marked reviewed.

The size of the physical address space of a processor is

bytes. The capacity of a cache memory unit is

bytes. The cache block size is 128 bytes. The cache memory unit can be built as a direct mapped cache or as a

-way set-associative cache, where

and

. Let the length of the TAG field be

bits for the direct mapped cache, and

bits for the set-associative cache.

Which one of the following options is true?

Your answerChoose one option.

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Consider a system with a processor and a 4 KB direct mapped cache with block size of 16 bytes. The system has a 16 MB physical memory. Four words P, Q, R, and S are accessed by the processor in the same order 10 times. That is, there are a total of 40 memory references in the sequence P, Q, R, S, P, Q, R, S,...

Assume that the cache memory is initially empty. The physical addresses of the words are given below (1 word =1 byte).

P: 0x845B32, Q: 0x845B26, R: 0x845B36, S: 0x846B32

Which of the following statements is/are true?

Note: 1K=2¹⁰ and 1M=2²⁰

Your answerSelect all correct options. You can choose more than one.

Every access to P results in a cache miss

Every access to R results in a cache hit

Every access to Q results in a cache miss

Except the first access to S, all subsequent accesses to S result in cache hits

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Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a translation lookaside buffer (TLB). Assume that when a page is evicted from the main memory, the corresponding blocks in the cache are marked as invalid.

For a given memory reference, which of the following sequences of events can NEVER happen?

Your answerSelect all correct options. You can choose more than one.

TLB miss, Page table hit, Cache hit

TLB hit, Page table miss, Cache hit

TLB miss, Page table miss, Cache hit

TLB miss, Page table miss, Cache miss

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Consider a system with 1 MB physical memory and a word length of 1 byte. The system uses a direct mapped cache, with block numbers starting from 0. The word with physical address 0xA2C28 is mapped to the cache block number 176₁₀. The maximum possible size of the cache (in KB) for this configuration is __________. (answer in integer)

Note: 1K=2¹⁰ and 1M=2²⁰

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Which of the following is/are part of an Instruction Set Architecture of a processor?

Your answerSelect all correct options. You can choose more than one.

The size of the cache memory

The clock frequency of the processor

The number of cache memory levels

The total number of registers

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Consider a memory system with 1M bytes of main memory and 16K bytes of cache memory. Assume that the processor generates 20-bit memory address, and the cache block size is 16 bytes. If the cache uses direct mapping, how many bits will be required to store all the tag values? [Assume memory is byte addressable, 1K=2^, 1M=2^.]

Your answerChoose one option.

6 × 2^

8 × 2^

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For a direct-mapped cache, 4 bits are used for the tag field and 12 bits are used to index into a cache block. The size of each cache block is one byte. Assume that there is no other information stored for each cache block.

Which ONE of the following is the CORRECT option for the sizes of the main memory and the cache memory in this system (byte addressable), respectively?

Your answerChoose one option.

64 KB and 4 KB

128 KB and 16 KB

64 KB and 8 KB

128 KB and 6 KB

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A computer has a memory hierarchy consisting of two-level cache (L1 and L2) and a main memory. If the processor needs to access data from memory, it first looks into L1 cache. If the data is not found in L1 cache, it goes to L2 cache. If it fails to get the data from L2 cache, it goes to main memory, where the data is definitely available. Hit rates and access times of various memory units are shown in the figure. The average memory access time in nanoseconds (ns) is ______. (rounded off to two decimal places)

Diagram for Computer Science and Information Technology question 53

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Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is 1 nanosecond (ns) and the “hit rate” for L1 cache is 90% while the processor is accessing the data from L1 cache. Whereas, for the second level (L2) cache, the “hit rate” is 80% and the “miss penalty” for transferring data from L2 cache to L1 cache is 10 ns. The “miss penalty” for the data to be transferred from main memory to L2 cache is 100 ns.

Then the average memory access time in this system in nanoseconds is __________. (rounded off to one decimal place)

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Consider two set-associative cache memory architectures: WB, which uses the write back policy, and WT, which uses the write through policy. Both of them use the LRU (Least Recently Used) block replacement policy. The cache memory is connected to the main memory. Which of the following statements is/are TRUE?

Your answerSelect all correct options. You can choose more than one.

A read miss in WB never evicts a dirty block

A read miss in WT never triggers a write back operation of a cache block to main memory

A write hit in WB can modify the value of the dirty bit of a cache block

A write miss in WT always writes the victim cache block to main memory before loading the missed block to the cache

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GATE CSE concept:cache PYQs

How to practice concept:cache

Question 38

Question 52

Question 54

Question 56

Question 28

Question 36

Question 39

Question 53

Question 55

Question 53