GATE CSE concept:main-memory PYQs & Answers

Questions 1–10 of 18. Imported answers require independent review unless marked reviewed.

Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a translation lookaside buffer (TLB). Assume that when a page is evicted from the main memory, the corresponding blocks in the cache are marked as invalid.

For a given memory reference, which of the following sequences of events can NEVER happen?

Your answerSelect all correct options. You can choose more than one.

TLB miss, Page table hit, Cache hit

TLB hit, Page table miss, Cache hit

TLB miss, Page table miss, Cache hit

TLB miss, Page table miss, Cache miss

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Consider a memory system with 1M bytes of main memory and 16K bytes of cache memory. Assume that the processor generates 20-bit memory address, and the cache block size is 16 bytes. If the cache uses direct mapping, how many bits will be required to store all the tag values? [Assume memory is byte addressable, 1K=2^, 1M=2^.]

Your answerChoose one option.

6 × 2^

8 × 2^

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For a direct-mapped cache, 4 bits are used for the tag field and 12 bits are used to index into a cache block. The size of each cache block is one byte. Assume that there is no other information stored for each cache block.

Which ONE of the following is the CORRECT option for the sizes of the main memory and the cache memory in this system (byte addressable), respectively?

Your answerChoose one option.

64 KB and 4 KB

128 KB and 16 KB

64 KB and 8 KB

128 KB and 6 KB

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A computer has a memory hierarchy consisting of two-level cache (L1 and L2) and a main memory. If the processor needs to access data from memory, it first looks into L1 cache. If the data is not found in L1 cache, it goes to L2 cache. If it fails to get the data from L2 cache, it goes to main memory, where the data is definitely available. Hit rates and access times of various memory units are shown in the figure. The average memory access time in nanoseconds (ns) is ______. (rounded off to two decimal places)

Diagram for Computer Science and Information Technology question 53

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Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is 1 nanosecond (ns) and the “hit rate” for L1 cache is 90% while the processor is accessing the data from L1 cache. Whereas, for the second level (L2) cache, the “hit rate” is 80% and the “miss penalty” for transferring data from L2 cache to L1 cache is 10 ns. The “miss penalty” for the data to be transferred from main memory to L2 cache is 100 ns.

Then the average memory access time in this system in nanoseconds is __________. (rounded off to one decimal place)

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Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?

Your answerChoose one option.

2,56,000

3,200

25,60,000

32,000

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Which one of the following statements is FALSE?

Your answerChoose one option.

In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a stolen cycle

For bulk data transfer, the burst mode of DMA has a higher throughput than the cycle stealing mode

Program I/O mechanism has a better CPU utilization than the interrupt driven I/O mechanism

The CPU can start executing in interrupt service routine faster with vectored interrupts than with non-vectored interrupts

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Consider two set-associative cache memory architectures: WB, which uses the write back policy, and WT, which uses the write through policy. Both of them use the LRU (Least Recently Used) block replacement policy. The cache memory is connected to the main memory. Which of the following statements is/are TRUE?

Your answerSelect all correct options. You can choose more than one.

A read miss in WB never evicts a dirty block

A read miss in WT never triggers a write back operation of a cache block to main memory

A write hit in WB can modify the value of the dirty bit of a cache block

A write miss in WT always writes the victim cache block to main memory before loading the missed block to the cache

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Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?

Your answerChoose one option.

DMA based I/O transfer

Interrupt driven I/O transfer

Polling based I/O transfer

Programmed I/O transfer

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Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back cache and WT is a write through cache. Which of the following statements is/are FALSE?

Your answerSelect all correct options. You can choose more than one.

Each cache block in WB and WT has a dirty bit.

Every write hit in WB leads to a data transfer from cache to main memory.

Eviction of a block from WT will not lead to data transfer from cache to main memory.

A read miss in WB will never lead to eviction of a dirt block from WB.

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GATE CSE concept:main-memory PYQs

How to practice concept:main-memory

Question 54

Question 36

Question 39

Question 53

Question 55

Question 11

Question 15

Question 53

Question 17

Question 24