Complete GATE CSE 2026 Paper 1 overview, original pages and practice · Timed previous-paper practice

Questions 37–39 of 65. Imported answers require review unless explicitly marked reviewed.

Paper practice 65 questionsPage 13 of 22

Question 37

Open question
CSMCQ2 marksNeeds review
Consider a 2-bit saturating up/down counter that performs the saturating up count when the input P is 0, and the saturating down count when P is 1. The Next State table of the counter is as shown. The counter is built as a synchronous sequential circuit using D flip-flops.
[Table: Input P, Current State Q₁ Q₀, Next State Q₁⁺ Q₀⁺; rows (P,Q₁,Q₀ → Q₁⁺,Q₀⁺): (0,0,0→0,1), (0,0,1→1,0), (0,1,0→1,1), (0,1,1→1,1), (1,0,0→0,0), (1,0,1→0,0), (1,1,0→0,1), (1,1,1→1,0).]
Which one of the following options corresponds to the expressions for the inputs of the D flip-flops, D₁ and D₀?
Your answerChoose one option.

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Question 38

Open question
CSMCQ2 marksNeeds review
The size of the physical address space of a processor is

bytes. The capacity of a cache memory unit is

bytes. The cache block size is 128 bytes. The cache memory unit can be built as a direct mapped cache or as a

-way set-associative cache, where

and

. Let the length of the TAG field be

bits for the direct mapped cache, and

bits for the set-associative cache.
Which one of the following options is true?
Your answerChoose one option.

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Question 39

Open question
CSMCQ2 marksNeeds review
Consider the following code snippet in C language that computes the number of nodes in a non-empty singly linked list pointed to by the pointer variable head.
struct node{
int elt;
struct node *next;
};

int getListSize (struct node *head)
{
if( E1 ) return 1;
return E2;
}
Which one of the following options gives the correct replacements for the expressions E1 and E2?
Your answerChoose one option.

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