GATE CSE · 2026 · CS
Question 37: Digital Logic
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Question 37
CSMCQ2 marksNeeds review
Consider a 2-bit saturating up/down counter that performs the saturating up count when the input P is 0, and the saturating down count when P is 1. The Next State table of the counter is as shown. The counter is built as a synchronous sequential circuit using D flip-flops.
[Table: Input P, Current State Q₁ Q₀, Next State Q₁⁺ Q₀⁺; rows (P,Q₁,Q₀ → Q₁⁺,Q₀⁺): (0,0,0→0,1), (0,0,1→1,0), (0,1,0→1,1), (0,1,1→1,1), (1,0,0→0,0), (1,0,1→0,0), (1,1,0→0,1), (1,1,1→1,0).]
Which one of the following options corresponds to the expressions for the inputs of the D flip-flops, D₁ and D₀?
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2026CS
GATE CSE 2026 · Paper 1
Computer Science and Information Technology · Original paper archive
- Section
- Computer Science and Information Technology
- Question type
- Multiple choice (MCQ)
- Marks
- 2 marks
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