GATE CSE 2026 Paper 1 — page 18

Questions 52–54 of 65. Imported answers require review unless explicitly marked reviewed.

Consider the following context-free grammar

In the above grammar,

is the start symbol,

and

are terminal symbols, and

and

are non-terminal symbols.

Let

be the language generated by the grammar

. For a string

, let

be the number of

’s in

and

be the number of

’s in

Which of the following statements is/are true?

Your answerSelect all correct options. You can choose more than one.

There is a string

such that

For every string

There is a string

such that

For every string

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Consider the following two syntax-directed definitions SD1 and SD2 for type declarations.

SD1 Grammar (G1) | Semantic Rules D → T V: D.type = T.type; V.type = T.type T → int: T.type = int T → float: T.type = float V → V₁ id: V₁.type = V.type; put(id.entry, V.type) V → id: put(id.entry, V.type)

SD2 Grammar (G2) | Semantic Rules D → D₁ id: D.type = D₁.type; put(id.entry, D₁.type) D → T id: D.type = T.type; put(id.entry, T.type) T → int: T.type = int T → float: T.type = float

D is the start symbol, and int, float and id are the terminals. The non-terminal V₁ is the same as V and the non-terminal D₁ is the same as D. Here, the subscript is used to differentiate the grammar symbol on the two sides of a production. The function put updates the symbol table with the type information for an identifier.

Let P and Q be the languages specified by grammars G1 and G2, respectively.

Which of the following statements is/are true?

Your answerSelect all correct options. You can choose more than one.

The languages P and Q are the same

SD2 is S-attributed and contains only synthesized attributes

SD1 is L-attributed and contains only inherited attributes

The specifications of SD1 and SD2 are such that the same entries get added to the symbol table

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Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a translation lookaside buffer (TLB). Assume that when a page is evicted from the main memory, the corresponding blocks in the cache are marked as invalid.

For a given memory reference, which of the following sequences of events can NEVER happen?

Your answerSelect all correct options. You can choose more than one.

TLB miss, Page table hit, Cache hit

TLB hit, Page table miss, Cache hit

TLB miss, Page table miss, Cache hit

TLB miss, Page table miss, Cache miss

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2026 · Paper 1

Question 52

Question 53

Question 54