GATE ECE 2021 Paper 1 — page 19

Questions 55–57 of 65. Imported answers require review unless explicitly marked reviewed.

A circuit with an ideal OPAMP is shown in the figure. A pulse

of 20 ms duration is applied to the input. The capacitors are initially uncharged.

Diagram for Electronics and Communication Engineering question 45

The output voltage

of this circuit at

(in integer) is ______ V.

You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answer

The propagation delay of the exclusive-OR (XOR) gate in the circuit in the figure is 3 ns. The propagation delay of all the flip-flops is assumed to be zero. The clock (Clk) frequency provided to the circuit is 500 MHz.

Diagram for Electronics and Communication Engineering question 46

Starting from the initial value of the flip-flop outputs

with

, the minimum number of triggering clock edges after which the flip-flop outputs

becomes 100 (in integer) is ______.

You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answer

The circuit in the figure contains a current source driving a load having an inductor and a resistor in series, with a shunt capacitor across the load. The ammeter is assumed to have zero resistance. The switch is closed at time

Diagram for Electronics and Communication Engineering question 47

Initially, when the switch is open, the capacitor is discharged and the ammeter reads zero ampere. After the switch is closed, the ammeter reading keeps fluctuating for some time till it settles to a final steady value. The maximum ammeter reading that one will observe after the switch is closed (rounded off to two decimal places) is ______ A.

You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answer

2021 · Paper 1

Question 45

Question 46

Question 47