GATE ECE · 2021 · EC
Question 46: Sequential circuits
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Question 46
ECNAT2 marksNeeds review
The propagation delay of the exclusive-OR (XOR) gate in the circuit in the figure is 3 ns. The propagation delay of all the flip-flops is assumed to be zero. The clock (Clk) frequency provided to the circuit is 500 MHz.
Starting from the initial value of the flip-flop outputs
with
, the minimum number of triggering clock edges after which the flip-flop outputs
becomes 100 (in integer) is ______.Log in to check the answer
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2021EC
GATE ECE 2021 · Paper 1
Electronics and Communication Engineering · Original paper archive
- Section
- Electronics and Communication Engineering
- Question type
- Numerical answer (NAT)
- Marks
- 2 marks
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