Electronics and Communication Engineering
2025 · Paper 1
Take it one question at a time. Try an answer, then check your understanding.
Complete GATE ECE 2025 Paper 1 overview, original pages and practice · Timed previous-paper practice
Questions 61–63 of 65. Imported answers require review unless explicitly marked reviewed.
Question 61
Open questionECNAT2 marksNeeds review
The diode in the circuit shown below is ideal. The input voltage (in Volts) is given by
, where time
is in seconds.The time duration (in ms, rounded off to two decimal places) for which the diode is forward biased during one period of the input is __________.
Log in to check the answer
You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 62
Open questionECNAT2 marksNeeds review
In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns.
The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is __________.
Log in to check the answer
You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 63
Open questionECNAT2 marksNeeds review
An ideal p-n junction germanium diode has a reverse saturation current of 10
A at 300 K.The voltage (in Volts, rounded off to two decimal places) to be applied across the junction to get a forward bias current of 100 mA at 300 K is ____.
(Consider the Boltzman constant
J/K and the charge of an electron
C.)Log in to check the answer
You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answer