Electronics and Communication Engineering
2026 · Paper 1
Take it one question at a time. Try an answer, then check your understanding.
Complete GATE ECE 2026 Paper 1 overview, original pages and practice · Timed previous-paper practice
Questions 49–51 of 65. Imported answers require review unless explicitly marked reviewed.
Question 49
Open questionECMCQ2 marksNeeds review
A shift-left Shift Register (SR) and a D flip-flop are connected to a synchronized clock as shown in the Figure. Assume that the SR and D flip-flops are initially cleared and the XOR gate has no propagation delay.
Which of the following options gives the correct binary representation (
) of the content of the shift register immediately after the 5th clock transition (positive edge)? 
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Open questionECMCQ2 marksNeeds review
A small signal source,
is applied to a BJT circuit as shown in the Figure.Assume zero source resistance,
V,
, Early voltage = 100 V and Thermal voltage = 25 mV. Effect of internal parasitic capacitances of the BJT may be neglected.Which expression is the best approximation of the output voltage
? 
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Open questionECMCQ2 marksNeeds review
Consider the two-port network as shown in the Figure.
Which of the following options provides the correct set of values of A, B, C and D parameters?
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