GATE CSE · 2023 · CS
Question 42: Computer Organization and Architecture
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Question 42
CSMCQ2 marksNeeds review
A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip select (CS) port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from IA11–IA0 are connected to the address port of these blocks. The chip select (CS) is active high.
The input memory address (IA11–IA0), in decimal, for the starting locations (Addr=0) of each block (indicated as X1, X2, X3, X4 in the figure are among the options given below. Which one of the following options is CORRECT?
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2023CS
GATE CSE 2023 · Paper 1
Computer Science and Information Technology · Original paper archive
- Section
- Computer Science and Information Technology
- Question type
- Multiple choice (MCQ)
- Marks
- 2 marks
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