GATE CSE · 2021 · CS
Question 55: Computer Organization and Architecture
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Question 55
CSNAT2 marksNeeds review
Consider the following instruction sequence where registers R1, R2 and R3 are general purpose and MEMORY[X] denotes the content at the memory location X.
Instruction | Semantics | Instruction Size (bytes) |
|---|---|---|
MOV R1, (500) | R1 ← MEMORY[500] | 4 |
MOV R2, (R3) | R2 ← MEMORY[R3] | 4 |
ADD R2, R1 | R2 ← R1+R2 | 2 |
MOV (R3), R2 | MEMORY[R3] ← R2 | 4 |
INC R3 | R3 ← R3+1 | 2 |
DEC R1 | R1 ← R1-1 | 2 |
BNZ 104 | Branch if not zero to the given absolute address | 2 |
HALT | Stop | 1 |
Assume that the content of the memory location 500 is 10, and the content of the register R3 is 300. The content of each of the memory locations from 300 to 3010 is 50. The instruction sequence starts from the memory location 100. All the numbers are in decimal format. Assume that the memory is byte addressable.
After the execution of the program, the content of memory location 3010 is __________.
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2021CS
GATE CSE 2021 · Paper 1
Computer Science and Information Technology · Original paper archive
- Section
- Computer Science and Information Technology
- Question type
- Numerical answer (NAT)
- Marks
- 2 marks
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