GATE IN · 2024 · IN
Question 42: Digital Electronics
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Question 42
INMCQ2 marksNeeds review
In the figure shown, the positive edge triggered D flip-flops are initially reset to Q = 0. The logic gates and the multiplexers have no propagation delay. After reset, a train of clock pulses (CLK) are applied. The logic states of the inputs DIN, S and the clock pulses are also shown in the figure. Assuming no timing violations, the sequence of output Y from the 3rd clock to the 5th clock,
is 
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2024IN
GATE IN 2024 · Paper 1
Instrumentation Engineering · Original paper archive
- Section
- Instrumentation Engineering
- Question type
- Multiple choice (MCQ)
- Marks
- 2 marks
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