GATE CSE · 2026 · CS
Question 60: Computer Organization and Architecture
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Question 60
CSNAT2 marksNeeds review
The EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithmetic and logic instructions. Let
denote the time taken by the EX stage to perform the operation for an instruction. For each instruction type, the values of
and
(the number of instructions of that type in a sequence of 100 instructions for a program P), are given in the table below. The duration of the pipeline clock cycle is 1 nanosecond. Assume that the latch time for the interstage buffers in the pipeline is negligible. Table (Instruction,
in nanoseconds,
): LOAD, 1.8, 15; MUL, 1.5, 10; IDIV, 2.5, 5; FADD, 1.7, 10; FSUB, 1.7, 5; FMUL, 2.8, 15; FDIV, 3.2, 5; All other instructions, Less than 1.0, 35. When program P is executed, the number of clock cycles for which the pipeline is stalled due to structural hazards in the EX stage is _____. (answer in integer)Log in to check the answer
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2026CS
GATE CSE 2026 · Paper 1
Computer Science and Information Technology · Original paper archive
- Section
- Computer Science and Information Technology
- Question type
- Numerical answer (NAT)
- Marks
- 2 marks
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