GATE CSE area:computing-and-data PYQs & Answers — Page 11

Questions 101–110 of 159. Imported answers require independent review unless marked reviewed.

Consider a computer system with a byte-addressable primary memory of size

bytes. Assume the computer system has a direct-mapped cache of size 32 KB (1 KB =

bytes), and each cache block is of size 64 bytes. The size of the tag field is ________ bits.

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Assume a two-level inclusive cache hierarchy, L1 and L2, where L2 is the larger of the two. Consider the following statements.

: Read misses in a write through L1 cache do not result in writebacks of dirty lines to the L2.

: Write allocate policy must be used in conjunction with write through caches and no-write allocate policy is used with writeback caches.

Which of the following statements is correct?

Your answerChoose one option.

is true and

is false

is false and

is true

is true and

is true

is false and

is false

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A TCP server application is programmed to listen on port number

on host

. A TCP client is connected to the TCP server over the network. Consider that while the TCP connection was active, the server machine

crashed and rebooted. Assume that the client does not use the TCP keepalive timer. Which of the following behaviors is/are possible?

Your answerSelect all correct options. You can choose more than one.

If the client was waiting to receive a packet, it may wait indefinitely.

The TCP server application on

can listen on

after reboot.

If the client sends a packet after the server reboot, it will receive a RST segment.

If the client sends a packet after the server reboot, it will receive a FIN segment.

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If the numerical value of a 2-byte signed integer on a little endian computer is 255 more than that on a big endian computer, which of the following choices represent(s) the unsigned integer on a little endian computer?

Your answerSelect all correct options. You can choose more than one.

0x665

0x001

0x423

0x100

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Consider two hosts

and

connected through a router

. The maximum transfer unit (MTU) value of the link between

and

is 1500 bytes, and between

and

is 820 bytes. A TCP segment of size 1400 bytes was transferred from

through

, with IP identification value as 0x1234. Assume that the IP header size is 20 bytes. Further, the packet is allowed to be fragmented, i.e., Don’t Fragment (DF) flag in the IP header is not set by

. Which of the following statements is/are correct?

Your answerSelect all correct options. You can choose more than one.

Two fragments are created at

and the IP datagram size carrying the second fragment is 620 bytes.

If the second fragment is lost,

will resend the fragment with the IP identification value 0x1234.

If the second fragment is lost,

is required to resend the whole TCP segment.

TCP destination port can be determined by analysing only the second fragment.

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Consider a computer network using the distance vector routing algorithm in its network layer. The partial topology of the network is as shown below.

Diagram for Computer Science and Information Technology question 45

The objective is to find the shortest-cost path from the router

to routers

and

. Assume that

does not initially know the shortest routes to

and

. Assume that

has three neighboring routers denoted as

, and

. During one iteration,

measures its distance to its neighbours

, and

as 3, 2, and 5, respectively. Router

gets routing vectors from its neighbours that indicate that the distance to router

from routers

, and

are 7, 6, and 5, respectively. The routing vector also indicates that the distance to router

from routers

, and

are 4, 6, and 8, respectively. Which of the following statement(s) is/are correct with respect to the new routing table of

, after update during this iteration?

Your answerSelect all correct options. You can choose more than one.

The distance from

will be stored as 10.

The distance from

will be stored as 7.

The next hop router for a packet from

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Consider a three-level page table to translate a 39-bit virtual address to a physical address as shown below.

Diagram for Computer Science and Information Technology question 48

The page size is 4KB (1KB =

bytes) and page table entry size at every level is 8 bytes. A process

is currently using 2GB (1GB =

bytes) virtual memory which is mapped to 2GB of physical memory. The minimum amount of memory required for the page table of

across all levels is ______ KB.

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Consider the sliding window flow-control protocol operating between a sender and a receiver over a full-duplex error-free link. Assume the following:

The time taken for processing the data frame by the receiver is negligible.

The time taken for processing the acknowledgement frame by the sender is negligible.

The sender has infinite number of frames available for transmission.

The size of the data frame is 2,000 bits and the size of the acknowledgement frame is 10 bits.

The link data rate in each direction is 1 Mbps (=

bits per second).

One way propagation delay of the link is 100 milliseconds.

The minimum value of the sender’s window size in terms of the number of frames (rounded to the nearest integer) needed to achieve a link utilization of 50% is __________.

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A five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds. The registers that are used between the pipeline stages have a delay of 5 nanoseconds each. The total time to execute 100 independent instructions on this pipeline, assuming there are no pipeline stalls, is __________ nanoseconds.

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Consider a pipelined processor with 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). Each stage of the pipeline, except the EX stage, takes one cycle. Assume that the ID stage merely decodes the instruction and the register read is performed in the EX stage. The EX stage takes one cycle for ADD instruction and two cycles for MUL instruction. Ignore pipeline register latencies.

Consider the following sequence of 8 instructions:

ADD, MUL, ADD, MUL, ADD, MUL, ADD, MUL

Assume that every MUL instruction is data-dependent on the ADD instruction just before it and every ADD instruction (except the first ADD) is data-dependent on the MUL instruction just before it. The speedup is defined as follows:

The speedup achieved in executing the given instruction sequence on the pipelined processor (rounded to 2 decimal places) is ____________.

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GATE CSE area:computing-and-data PYQs

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