GATE CSE area:computing-and-data PYQs & Answers — Page 13

Questions 121–130 of 159. Imported answers require independent review unless marked reviewed.

Consider a page system that uses 1-level page table residing in main memory and a TLB for address translation. Each main memory access takes 100 ns and TLB lookup takes 20 ns. Each page transfer to/from the disk takes 500 ns. Assume that the TLB hit ratio is 95%, page fault rate is 10%. Assume that for 20% of the total page faults, a dirty page has to be written back to disk before the required page is read in from disk. TLB update time is negligible. The average memory access time in ns (round off to 1 decimal places) is ______.

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Consider a TCP connection between a client and a server with the following specifications: the round trip time is 6 ms, the size of the receiver advertised window is 50 KB, slow-start threshold at the client is 32 KB, and the maximum segment size is 2 KB. The connection is established at

. Assume that there are no timeouts and errors during transmission. Then the size of the congestion window (in KB) at time

ms after all acknowledgments are processed is ______.

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A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor?

Your answerChoose one option.

24 bits and 0 bits

28 bits and 4 bits

24 bits and 4 bits

28 bits and 0 bits

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The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by A₁₅ to A₀. What is the range of addresses (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?

Diagram for Computer Science and Information Technology question 2

Your answerChoose one option.

C800 to CFF

CA00 to CAFF

C800 to C8FF

DA00 to DFF

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Which of the following protocol pairs can be used to send and retrieve e-mails (in that order)?

Your answerChoose one option.

IMAP, POP3

SMTP, POP3

SMTP, MIME

IMAP, SMTP

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Consider three machines M, N, and P with IP addresses 100.10.5.2, 100.10.5.5, and 100.10.5.6 respectively. The subnet mask is set to 255.255.255.252 for all the three machines. Which one of the following is true?

Your answerChoose one option.

M, N, and P all belong to the same subnet

Only M and N belong to the same subnet

Only N and P belong to the same subnet

M, N, and P belong to three different subnets

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Suppose that in an IP-over-Ethernet network, a machine X wishes to find the MAC address of another machine Y in its subnet. Which one of the following techniques can be used for this?

Your answerChoose one option.

X sends an ARP request packet to the local gateway’s IP address which then finds the MAC address of Y and sends to X

X sends an ARP request packet to the local gateway’s MAC address which then finds the MAC address of Y and sends to X

X sends an ARP request packet with broadcast MAC address in its local subnet

X sends an ARP request packet with broadcast IP address in its local subnet

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Assume that in a certain computer, the virtual addresses are 64 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 8 kB and the word size is 4 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 128 valid entries. At most how many distinct virtual addresses can be translated without any TLB miss?

Your answerChoose one option.

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A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a 60-MHz clock. To service a cache miss, the memory controller first takes 1 cycle to accept the starting address of the block, it then takes 3 cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of 1 word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is ________ × 10⁶ bytes/sec.

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Consider that 15 machines need to be connected in a LAN using 8-port Ethernet switches. Assume that these switches do not have any separate uplink ports. The minimum number of switches needed is ________.

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GATE CSE area:computing-and-data PYQs

Question 53

Question 55

Question 1

Question 2

Question 16

Question 28

Question 29

Question 33

Question 45

Question 49