GATE CSE area:computing-and-data PYQs & Answers — Page 2

Questions 11–20 of 159. Imported answers require independent review unless marked reviewed.

The size of the physical address space of a processor is

bytes. The capacity of a cache memory unit is

bytes. The cache block size is 128 bytes. The cache memory unit can be built as a direct mapped cache or as a

-way set-associative cache, where

and

. Let the length of the TAG field be

bits for the direct mapped cache, and

bits for the set-associative cache.

Which one of the following options is true?

Your answerChoose one option.

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Consider the transmission of data bits 1100101 over a link that uses Cyclic Redundancy Check (CRC) code for error detection. If the generator bit pattern is given to be 1001, which one of the following options shows the remainder bit pattern appended to the data bits before transmission?

Your answerChoose one option.

011

101

000

100

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A TCP sender successfully establishes a connection with a TCP receiver and starts the transmission of segments. The TCP congestion control mechanism’s slow-start threshold is set to 1000 segments. Assume that the round-trip time is fixed at 1 milisecond. Assume that the sender always has data to send, the segments are numbered from 1, and no segment is lost. Let

denote the time (in miliseconds) at which the transmission of segment number 2000 starts. Which one of the following options is correct?

Your answerChoose one option.

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Consider a processor that has 16 general purpose registers and it uses 2-byte instruction format for all its instructions. Variable-sized opcodes are permitted. There are three different types of instructions; M-type, R-type, and C-type. Each M-type instruction has 2 register operands and a 6-bit immediate operand. Each R-type instruction has 3 register operands. Each C-type instruction has a register operand and a 6-bit offset value. If there are 2 unique M-type opcodes and 7 unique R-type opcodes, which one of the following options gives the maximum number of unique opcodes possible for C-type instructions?

Your answerChoose one option.

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Consider the implementation of sliding window protocol over a lossless link, with a window size of

frames, where each frame is of size 1000 bits (including header). The bandwidth of the link is 100 kbps (

) and the one-way propagation delay is 100 miliseconds. Assume that processing times at the sender and receiver are zero and the transmission time of acknowledgments is also zero. Which one of the following options gives the minimum size of

(in number of frames) required to achieve 100% link utilization?

Your answerChoose one option.

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Consider a system with a processor and a 4 KB direct mapped cache with block size of 16 bytes. The system has a 16 MB physical memory. Four words P, Q, R, and S are accessed by the processor in the same order 10 times. That is, there are a total of 40 memory references in the sequence P, Q, R, S, P, Q, R, S,...

Assume that the cache memory is initially empty. The physical addresses of the words are given below (1 word =1 byte).

P: 0x845B32, Q: 0x845B26, R: 0x845B36, S: 0x846B32

Which of the following statements is/are true?

Note: 1K=2¹⁰ and 1M=2²⁰

Your answerSelect all correct options. You can choose more than one.

Every access to P results in a cache miss

Every access to R results in a cache hit

Every access to Q results in a cache miss

Except the first access to S, all subsequent accesses to S result in cache hits

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Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a translation lookaside buffer (TLB). Assume that when a page is evicted from the main memory, the corresponding blocks in the cache are marked as invalid.

For a given memory reference, which of the following sequences of events can NEVER happen?

Your answerSelect all correct options. You can choose more than one.

TLB miss, Page table hit, Cache hit

TLB hit, Page table miss, Cache hit

TLB miss, Page table miss, Cache hit

TLB miss, Page table miss, Cache miss

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A system has a Translation Lookaside Buffer (TLB) that has a reach of 1 MB. TLB reach is defined as the total amount of physical memory that can be accessed through the TLB entries. The paging system uses pages of size 4 KB. The virtual address space is 64 GB and physical address space is 1 GB. If each TLB entry stores a 4-bit process id, page number, frame number, and a 2-bit control field, then the size of the TLB (in bytes) is __________. (answer in integer)

Note: 1K=2¹⁰, 1M=2²⁰, 1G=2³⁰

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An ISP having an address block 202.16.0.0/15 assigns a block of 600 IP addresses to a client, using the classless inter domain routing (CIDR) super-netting approach. Which of the following address blocks can be assigned by the ISP?

Your answerSelect all correct options. You can choose more than one.

202.16.0.0/19

202.17.64.0/19

202.16.32.0/19

202.17.24.0/19

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Consider a system with 1 MB physical memory and a word length of 1 byte. The system uses a direct mapped cache, with block numbers starting from 0. The word with physical address 0xA2C28 is mapped to the cache block number 176₁₀. The maximum possible size of the cache (in KB) for this configuration is __________. (answer in integer)

Note: 1K=2¹⁰ and 1M=2²⁰

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GATE CSE area:computing-and-data PYQs

Question 38

Question 43

Question 44

Question 44

Question 45

Question 52

Question 54

Question 54

Question 56

Question 56